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参数资料
型号： P89V662FBC,557
厂商： NXP Semiconductors
文件页数： 65/90页
文件大小： 0K
描述： IC 80C51 MCU FLASH 32K 44-TQFP
产品培训模块： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装： 800
系列： 89V
核心处理器： 8051
芯体尺寸： 8-位
速度： 40MHz
连通性： I²C，SPI，UART/USART
外围设备： POR，PWM，WDT
输入/输出数： 36
程序存储器容量： 32KB（32K x 8）
程序存储器类型： 闪存
RAM 容量： 1K x 8
电压 - 电源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 44-TQFP
包装： 托盘
配用： 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名称： 568-2435
568-2435-ND
568-8271
935280832557
P89V662FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
68 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.13 Power-saving modes
The device provides two power saving modes of operation for applications where power
consumption is critical. The two modes are idle and power-down, see Table 67.
Table 61.
IP0H - Interrupt priority 0 high register (address B7H) bit allocation
Not bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
PT2H
PPCH
PS1H
PS0H
PT1H
PX1H
PT0H
PX0H
Table 62.
IP0H - Interrupt priority 0 high register (address B7H) bit description
Bit
Symbol
Description
7
PT2H
Timer 2 Interrupt Priority High Bit.
6
PPCH
PCA Interrupt Priority High Bit.
5PS1H
I2C-bus Interrupt Priority High Bit (primary).
4
PS0H
Serial Port Interrupt Priority High Bit.
3
PT1H
Timer 1 Interrupt Priority High Bit.
2
PX1H
External Interrupt 1 Priority High Bit.
1
PT0H
Timer 0 Interrupt Priority High Bit.
0
PX0H
External Interrupt 0 Priority High Bit.
Table 63.
IP1 - Interrupt priority 1 register (address 91H) bit allocation
Bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
-
PS3
PS2
Table 64.
IP1 - Interrupt priority 1 register (address 91H) bit description
Bit
Symbol
Description
7 to 2
-
Reserved for future use. Should be set to ‘0’ by user programs.
1
PS3
SPI Interrupt Priority Low Bit.
0PS2
I2C-bus Interrupt Priority 1 Low Bit (secondary).
Table 65.
IP1H - Interrupt priority 1 high register (address 92H) bit allocation
Not bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
-
PS3H
PS2H
Table 66.
IP1H - Interrupt priority 1 high register (address 92H) bit description
Bit
Symbol
Description
7 to 2
-
Reserved for future use. Should be set to ‘0’ by user programs.
1
PS3H
SPI Interrupt Priority High Bit.
0PS2H
I2C-bus Interrupt Priority High Bit (secondary).
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