参数资料
型号: PA28F200BX-B120
厂商: INTEL CORP
元件分类: PROM
英文描述: 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
中文描述: 128K X 16 FLASH 12V PROM, 120 ns, PDSO44
封装: 1.110 X 0.525 INCH, PLASTIC, SOP-44
文件页数: 4/48页
文件大小: 562K
代理商: PA28F200BX-B120
28F200BX-T/B, 28F002BX-T/B
The
Status Register (SR)
indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.
Maximum Access Time of
60 ns (t
ACC
)
is achieved
over the commercial temperature range (0
§
C to
70
§
C), 5% V
CC
supply voltage range (4.75V to
5.25V) and 30 pF output load. Refer to Figure 19;
t
ACC
vs Output Load Capacitance for larger output
loads. Maximum Access Time of
80 ns (t
ACC
)
is
achieved over the commercial temperature range,
10% V
CC
supply range (4.5V to 5.5V) and 100 pF
output load.
I
PP
maximum Program current is 40 mA for x16
operation and 30 mA for x8 operation. I
PP
Erase
current is 30 mA maximum. V
PP
erase and pro-
gramming voltage is 11.4V to 12.6V (V
PP
e
12V
g
5%) under all operating conditions.
As an op-
tion, V
PP
can also vary between 10.8V to 13.2V (V
PP
e
12V
g
10%) with a guaranteed number of 100
block erase cycles.
Typical I
CC
Active Current of 25 mA
is achieved
for the x16 products (28F200BX),
typical I
CC
Active
Current of 20 mA
is achieved for the x8 products
(28F200BX, 28F002BX). Refer to the I
CC
active cur-
rent derating curves in this datasheet.
The 2-Mbit boot block flash family is also designed
with an Automatic Power Savings (APS) feature to
minimize system battery current drain and allow for
very low power designs. Once the device is ac-
cessed to read array data, APS mode will immedi-
ately put the memory in static mode of operation
where I
CC
active current is typically 1 mA until the
next read is initiated.
When the CE
Y
and RP
Y
pins are at V
CC
and the
BYTE
Y
pin (28F200BX-only) is at either V
CC
or
GND the
CMOS Standby
mode is enabled where
I
CC
is typically 50
m
A.
A
Deep Power-Down Mode
is enabled when the
RP
Y
pin is at ground minimizing power consumption
and providing write protection during power-up con-
ditions.
I
CC
current
during deep power-down mode
is
0.20
m
A typical
. An initial maximum access time
or Reset Time of 300 ns is required from RP
Y
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 215 ns until
writes to the Command User Interface are recog-
nized. When RP
Y
is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature pre-
vents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RP
Y
to reset the memory to nor-
mal read mode upon activation of the Reset pin.
With on-chip program/erase automation in the
2-Mbit family and the RP
Y
functionality for data pro-
tection, when the CPU is reset and even if a program
or erase command is issued, the device will not rec-
ognize any operation until RP
Y
returns to its normal
state.
For the 28F200BX, Byte-wide or Word-wide In-
put/Output Control
is possible by controlling the
BYTE
Y
pin. When the BYTE
Y
pin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through DQ
[
0:7
]
. During the byte-
wide mode, DQ
[
8:14
]
are tri-stated and DQ15/A
b
1
becomes the lowest order address pin. When the
BYTE
Y
pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DQ
[
0:15
]
.
1.3 Applications
The 2-Mbit boot block flash family combines high
density, high performance, cost-effective flash mem-
ories with blocking and hardware protection capabili-
ties. Its flexibility and versatility will reduce costs
throughout the product life cycle. Flash memory is
ideal for Just-In-Time production flow, reducing sys-
tem inventory and costs, and eliminating component
handling during the production phase. During the
product life cycle, when code updates or feature en-
hancements become necessary, flash memory will
reduce the update costs by allowing either a user-
performed code change via floppy disk or a remote
code change via a serial link. The 2-Mbit boot block
flash family provides full function, blocked flash
memories suitable for a wide range of applications.
These applications include
Extended PC BIOS,
Digital Cellular Phone
program and data storage,
Telecommunication
boot/firmware, and various
other embedded applications where both program
and data storage are required.
Reprogrammable systems such as personal com-
puters, are ideal applications for the 2-Mbit flash
products. Portable and handheld personal computer
applications are becoming more complex with the
addition of power management software to take ad-
vantage of the latest microprocessor technology,
the availability of ROM-based application software,
pen tablet code for electronic hand writing, and diag-
nostic code. Figure 1 shows an example of a
28F200BX-T application.
This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped. The 2-Mbit flash products
provide an inexpensive update solution for the note-
book and handheld personal computers while ex-
tending their product lifetime. Furthermore, the
2-Mbit flash products’ power-down mode provides
added flexibility for these battery-operated portable
designs which require operation at very low power
levels.
4
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