28F200BX-T/B, 28F002BX-T/B
28F002BX Products
The manufacturer and device codes are also read
via the CUI or by taking the A9 pin to 12V. Writing
90H to the CUI places the device into Intelligent
Identifier read mode. A read of location 00000H out-
puts the manufacturer’s identification code, 89H,
and location 00001H outputs the device code; 7CH
for 28F002BX-T, 7DH for 28F002BX-B.
4.4 Write Operations
Commands are written to the CUI using standard mi-
croprocessor write timings. The CUl serves as the
interface between the microprocessor and the inter-
nal chip operation. The CUI can decipher Read Ar-
ray, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program com-
mands. In the event of a read command, the CUI
simply points the read path at either the array, the
intelligent identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state ma-
chine that a write or erase has been requested. Dur-
ing a program cycle, the Write State Machine will
control the program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task, it will allow the CUI to respond to its full com-
mand set. The CUI will stay in the current command
state until the microprocessor issues another com-
mand.
The CUI will successfully initiate an erase or write
operation only when V
PP
is within its voltage range.
Depending upon the application, the system design-
er may choose to make the V
PP
power supply
switchable, available only when memory updates
are desired. The system designer can also choose
to ‘‘hard-wire’’ V
PP
to 12V. The 2 Mbit boot block
flash family is designed to accommodate either de-
sign practice. It is recommended that RP
Y
be tied to
logical Reset for data protection during unstable
CPU reset function as described in the ‘‘Product
Family Overview’’ section.
4.4.1 BOOT BLOCK WRITE OPERATIONS
In the case of Boot Block modifications (write and
erase), RP
Y
is set to V
HH
e
12V typically, in addi-
tion to V
PP
at high voltage. However, if RP
Y
is not at
V
HH
when a program or erase operation of the boot
block is attempted, the corresponding status register
bit (Bit 4 for Program and Bit 5 for Erase, refer to
Table 5 for Status Register Definitions) is set to indi-
cate the failure to complete the operation.
4.4.2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a ‘‘1’’, which will also allow the CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
4.4.2.1 Command Set
Command
Codes
Device Mode
00
10
20
40
50
70
90
B0
D0
FF
Invalid/Reserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Erase Resume/Erase Confirm
Read Array
4.4.2.2 Command Function Descriptions
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the 2-Mbit
boot block flash family commands.
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