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参数资料
| 型号： | PA28F400BX-B80 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 256K X 16 FLASH 12V PROM, 80 ns, PDSO40 |
| 封装： | 1.110 X 0.525 INCH, PLASTIC, SOP-40 |
| 文件页数： | 10/50页 |
| 文件大小： | 559K |
| 代理商： | PA28F400BX-B80 |
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28F400BX-T/B, 28F004BX-T/B
1.6 28F004BX Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
18
I
ADDRESS INPUTS
for memory addresses. Addresses are internally latched during
a write cycle.
A
9
I
ADDRESS INPUT:
When A
9
is at 12V the signature mode is accessed. During this
mode A
0
decodes between the manufacturer and device ID’s.
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE
Y
and WE
Y
cycle
during a program command. Inputs commands to the command user interface when
CE
Y
and WE
Y
are active. Data is internally latched during the write and program
cycles. Outputs array, Intelligent Identifier and status register data. The data pins
float to tri-state when the chip is deselected or the outputs are disabled.
DQ
0
–DQ
7
I/O
CE
Y
I
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE
Y
is active low; CE
Y
high deselects the memory device and
reduces power consumption to standby levels. If CE
Y
and RP
Y
are high, but not at
a CMOS high level, the standby current will increase due to current flow through the
CE
Y
and RP
Y
input stages.
RP
Y
I
RESET/DEEP POWERDOWN:
Provides Three-State control. Puts the device in
deep power-down mode. Locks the Boot Block from program/erase.
When RP
Y
is at logic high level and equals 6.5V maximum the Boot Block is locked
and cannot be programmed or erased.
When RP
Y
e
11.4V minimum the Boot Block is unlocked and can be programmed
or erased.
When RP
Y
is at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power transitions.
When RP
Y
transitions from logic low to logic high, the flash memory enters the
read-array mode.
OE
Y
I
OUTPUT ENABLE:
Gates the device’s outputs through the data buffers during a
read cycle. OE
Y
is active low.
WE
Y
I
WRITE ENABLE:
Controls writes to the Command Register and array blocks. WE
Y
is active low. Addresses and data are latched on the rising edge of the WE
Y
pulse.
V
PP
PROGRAM/ERASE POWER SUPPLY:
For erasing memory array blocks or
programming data in each block.
NOTE:
V
PP
k
V
PPLMAX
memory contents cannot be altered.
V
CC
DEVICE POWER SUPPLY (5V
g
10%, 5V
g
5%)
GND
GROUND:
For all internal circuitry.
NC
NO CONNECT:
Pin may be driven or left floating.
DU
DON’T USE PIN:
Pin should not be connected to anything.
10
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PA28F400BX-T120 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400BX-T60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400BX-T70 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8/x16 Flash EEPROM |
| PA28F400BX-T80 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400CV-B60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
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