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参数资料
| 型号： | PA28F800CV-B60 |
| 厂商： | Intel Corp. |
| 英文描述： | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 2兆位SmartVoltage启动块闪存系列 |
| 文件页数： | 24/55页 |
| 文件大小： | 638K |
| 代理商： | PA28F800CV-B60 |
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2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
24
SEE NEW DESIGN RECOMMENDATIONS
SR.7 =
0
1
Start
Write 20H,
Block Address
Write D0H and
Block Address
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
1
0
Read Status Register
Data (See Above)
1
0
Read Status
Register
V
PP
Range Error
Suspend
Erase
Suspend Erase
Loop
YES
NO
1
0
Command Sequence
Error
SR.3 =
SR.5 =
SR.4,5 =
Block Erase Error
Bus
Operation
Command
Comments
Standby
Check SR.4,5
Both 1 = Command Sequence Error
Standby
Check SR.3
1 = V
PP
Low Detect
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.5 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erase before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Check SR.5
1 = Block Erase Error
Standby
Bus
Operation
Command
Comments
Write
Write
Erase Setup
Read
Data = 20H
Addr = Within Block to Be Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase, or after a
sequence of block erasures.
Write FFH after the last operation to reset device to read array mode.
Status Register Data Toggle CE#
or OE# to Update Status Register
Standby
Erase
Confirm
Data = D0H
Addr = Within Block to Be Erased
Block Erase Successful
0530_10
Figure 10. Automated Block Erase Flowchart
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