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参数资料
| 型号： | PA7024S-15 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Electrically Erasable Logic Array |
| 中文描述： | 电可擦除可编程逻辑阵列 |
| 文件页数： | 5/6页 |
| 文件大小： | 427K |
| 代理商： | PA7024S-15 |
5 of 6
PA7024
Sequential Timing - Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for
periods less than 20ns.
2. Test points for Clock and V
CC
in t
R
,t
F
,t
CL
,t
CH
, and t
RESET
are referenced
at 10% and 90% levels.
3. I/O pins are 0V or V
CC
.
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
6. Test conditions assume: signal transition times of 5ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless otherwise
specified).
7. t
OE
is measured from input transition to V
REF
±0.1V (See test loads for
V
REF
value). t
OD
is measured from input transition to V
OH
-0.1Vor V
OL
+0.1V.
8. “System-clock” refers to pin 1 or 13 (2 or 16 PLCC) high speed clocks.
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. I
CC
for a typical application: This parameter is tested with the device
programmed as a 10-bit D-type counter.
12. Test loads are specified in Section 5 of this Data Book.
13. “Async. clock” refers to the clock from the Sum term (OR gate).
14. The “LCC” term indicates that the timing parameter is applied to the
LCC register. The “IOC” term indicates that the timing parameter is
applied to the IOC register. The “LCC/IOC/INC” term indicates that the
timing parameter is applied to both the LCC, IOC and INC registers.
15. The term “Input” without any reference to another term refers to an
(external) input pin.
16. The parameter t
SPI
indicates that the PCLK signal to the IOC register is
always slower than the data from the pin or input by the absolute value
of (t
SK
-t
PK
-t
IA
). This means that no set-up time for the data from the
pin or input is required, i.e. the external data and clock can be sent to
the device simultaneously. Additionally, the data from the pin must
remain stable for t
HPI
time, i.e. to wait for the PCLK signal to arrive at
the IOC register.
17. Typical (typ) I
CC
is measured at T
A
=25°C, Freq = 25MHz, V
CC
=5V.
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| PA7024S-20 | Programmable Electrically Erasable Logic Array |
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| PA7024J-15 | Programmable Electrically Erasable Logic Array |
| PA7024 | Programmable Electrically Erasable Logic Array |
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相关代理商/技术参数 |
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|---|---|
| PA7024S-20 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Programmable Electrically Erasable Logic Array |
| PA7024S-25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| PA7024SI-25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Programmable Electrically Erasable Logic Array |
| PA7025 | 制造商:Electro Switch Corp 功能描述: |
| PA7040C-1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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