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参数资料
| 型号： | PALCE16V8 |
| 厂商： | Lattice Semiconductor Corporation |
| 英文描述： | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| 中文描述： | 电子工程的CMOS零功率20引脚通用可编程阵列逻辑 |
| 文件页数： | 4/32页 |
| 文件大小： | 634K |
| 代理商： | PALCE16V8 |
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12
PALCE16V8H-5/7 (Com’l)
USE
GAL
DEVICES
FOR
NEW
DESIGNS
CAPACITANCE1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are dened under best case conditions. Future process improvements
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modied where
frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25 °C,
5
pF
COUT
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
Parameter
Symbol
Parameter Description
-5
-7
Unit
Min 2
Max
Min 2
Max
tPD
Input or Feedback to Combinatorial Output
1
5
3
7.5
ns
tS
Setup Time from Input or Feedback to Clock
3
5
ns
tH
Hold Time
0
ns
tCO
Clock to Output
1415
ns
tSKEWR
Skew Between Registered Outputs (Note 3)
1
ns
tWL
Clock Width
LOW
3
4
ns
tWH
HIGH
3
4
ns
fMAX
Maximum Frequency
(Note 4)
External Feedback
1/(tS+tCO)
142.8
100
MHz
Internal Feedback (fCNT)
1/(tS+tCF) (Note 5)
166
125
MHz
No Feedback
1/(tWH+tWL)
166
125
MHz
tPZX
OE to Output Enable
1616
ns
tPXZ
OE to Output Disable
1516
ns
tEA
Input to Output Enable Using Product Term Control
2639
ns
tER
Input to Output Disable Using Product Term Control
2539
ns
相关PDF资料 |
PDF描述 |
|---|---|
| PALCE20V8H-10JC/4 | EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8H-7PC/5 | EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8H-15PI/4 | EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8Q-20PI/4 | EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8H-25PI/4 | EE CMOS 24-Pin Universal Programmable Array Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PALCE16V8 AND PALCE16V8Z FAMILIES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EE CMOS (Zero-Power) 20-Pin Universal Programmable Array Logic |
| PALCE16V8-10 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Flash-Erasable Reprogrammable CMOS PAL Device |
| PALCE16V8100DMB | 制造商:CYPRESS 功能描述:* |
| PALCE16V8-10DMB | 制造商:Cypress Semiconductor 功能描述: |
| PALCE16V8-10JC | 制造商:Cypress Semiconductor 功能描述: |
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