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参数资料
| 型号： | PALCE16V8H-15PC/4 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| 中文描述： | EE PLD, 15 ns, PDIP20 |
| 封装： | PLASTIC, DIP-20 |
| 文件页数： | 12/32页 |
| 文件大小： | 635K |
| 代理商： | PALCE16V8H-15PC/4 |
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PALCE16V8 and PALCE16V8Z Families
USE
GAL
DEVICES
FOR
NEW
DESIGNS
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the
PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z
has zero standby power and an unused product term disable feature for reduced power
consumption. It has eight independently congurable macrocells (MC0-MC7). Each macrocell can
be congured as registered output, combinatorial output, combinatorial I/O or dedicated input.
The programming matrix implements a programmable AND logic array, which drives a xed OR
logic array. Buffers for device inputs have complementary outputs to provide user-
programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK)
and output enable (OE), respectively, for all ip-ops.
Unused input pins should be tied directly to VCC or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE16V8 are automatically congured from the user’s
design specication. The design specication is processed by development software to verify
the design and create a programming le (JEDEC). This le, once downloaded to a programmer,
congures the device according to the user’s desired function.
The user is given two design options with the PALCE16V8. First, it can be programmed as a
standard PAL device from the PAL16R8 series. The PAL programmer manufacturer will supply
device codes for the standard PAL device architectures to be used with the PALCE16V8.
The programmer will program the PALCE16V8 in the corresponding architecture. This allows
the user to use existing standard PAL device JEDEC les without making any changes to them.
Programmable AND Array
32 x 64
MACRO
MC0
MACRO
MC1
MACRO
MC2
MACRO
MC3
MACRO
MC4
MACRO
MC5
MACRO
MC6
MACRO
MC7
OE
/I9
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
8
I1 – I8
CLK/I0
16493E-1
相关PDF资料 |
PDF描述 |
|---|---|
| PALCE16V8Q-15PC/4 | KPTC 3C 3#20 SKT PLUG |
| PALCE16V8H-25PC/4 | KPT 4C 4#20 PIN PLUG |
| PALCE16V8Q-25PC/4 | KPTC 4C 4#20 PIN PLUG |
| PALCE16V8H-5JC/5 | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| PALCE16V8Q-20JI/4 | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PALCE16V8H-15PC5 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20-Pin Universal Programmable Array Logic |
| PALCE16V8H-15PI | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20 PIN UNIVERSAL PROGRAMMABLE ARRAY LOGIC |
| PALCE16V8H-15PI/4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALCE16V8H-15PI4 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20-Pin Universal Programmable Array Logic |
| PALCE16V8H-15PI5 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20-Pin Universal Programmable Array Logic |
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