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参数资料
| 型号： | PALCE16V8H-25PI/4 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| 中文描述： | EE PLD, 25 ns, PDIP20 |
| 封装： | PLASTIC, DIP-20 |
| 文件页数： | 27/32页 |
| 文件大小： | 635K |
| 代理商： | PALCE16V8H-25PI/4 |
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4
PALCE16V8 and PALCE16V8Z Families
USE
GAL
DEVICES
FOR
NEW
DESIGNS
Registered Output Conguration
The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered
conguration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1x. The ip-op is loaded on the LOW-to-HIGH transition of CLK. The feedback
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Congurations
The PALCE16V8 has three combinatorial output congurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 0. All eight product terms are available
to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK
and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin
1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0.
Combinatorial I/O in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are
available to the OR gate. The eighth product term is used to enable the output buffer. The signal
at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to
be used as an input.
Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as
inputs. Pin 1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Dedicated Input Conguration
The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. Except
for MC0 and MC7, the feedback signal is an adjacent I/O. For MC0 and MC7, the feedback signals
are pins 1 and 11. These congurations are summarized in Table 1 and illustrated in Figure 2.
Table 1. Macrocell Conguration
SG0
SG1
SL0X
Cell
Conguration
Devices
Emulated
SG0
SG1
SL0X
Cell
Conguration
Devices
Emulated
Device Uses Registers
Device Uses No Registers
0
1
0
Registered Output
PAL16R8, 16R6,
16R4
100
Combinatorial
Output
PAL10H8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
011
Combinatorial
I/O
PAL16R6, 16R4
1
0
1
Input
PAL12H6, 14H4,
16H2, 12L6, 14L4,
16L2
111
Combinatorial
I/O
PAL16L8
相关PDF资料 |
PDF描述 |
|---|---|
| PALCE16V8Q-25PI/4 | KPT 5C 5#16 SKT RECP |
| PALCE16V8H-15PC/4 | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| PALCE16V8Q-15PC/4 | KPTC 3C 3#20 SKT PLUG |
| PALCE16V8H-25PC/4 | KPT 4C 4#20 PIN PLUG |
| PALCE16V8Q-25PC/4 | KPTC 4C 4#20 PIN PLUG |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PALCE16V8H-25PI5 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20-Pin Universal Programmable Array Logic |
| PALCE16V8H-25SC | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20 PIN UNIVERSAL PROGRAMMABLE ARRAY LOGIC |
| PALCE16V8H-25SC/4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述: |
| PALCE16V8H-25SC4 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20-Pin Universal Programmable Array Logic |
| PALCE16V8H-25SC5 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20-Pin Universal Programmable Array Logic |
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