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参数资料
| 型号： | PALCE16V8H-7PC/5 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| 中文描述： | EE PLD, 7.5 ns, PDIP20 |
| 封装： | PLASTIC, DIP-20 |
| 文件页数： | 23/32页 |
| 文件大小： | 635K |
| 代理商： | PALCE16V8H-7PC/5 |
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PALCE16V8 and PALCE16V8Z Families
3
USE
GAL
DEVICES
FOR
NEW
DESIGNS
Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the
PALCE16V8 device code. This option allows full utilization of the macrocell.
CONFIGURATION OPTIONS
Each macrocell can be congured as one of the following: registered output, combinatorial
output, combinatorial I/O, or dedicated input. In the registered output conguration, the output
buffer is enabled by the OE pin. In the combinatorial conguration, the buffer is either controlled
by a product term or always enabled. In the dedicated input conguration, it is always disabled.
With the exception of MC0 and MC7, a macrocell congured as a dedicated input derives the
input signal from an adjacent I/O. MC0 derives its input from pin 11 (OE) and MC7 from pin 1
(CLK).
The macrocell congurations are controlled by the conguration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0
determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will
emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0x, in
conjunction with SG1, selects the conguration of the macrocell, and SL1x sets the output as
either active low or active high for the individual macrocell.
The conguration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In
MC0 and MC7, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being
the adjacent pin for MC7 and OE the adjacent pin for MC0.
Figure 1. PALCE16V8 Macrocell
1 1
0 X
1 0
*SG1
SG1
SL0X
DQ
Q
1 0
1 1
0 X
1 1
1 0
0 0
0 1
VCC
CLK
SL0X
OE
To
Adjacent
Macrocell
From
Adjacent
Pin
1 1
0 X
1 0
SL1X
I/OX
16493E-2
*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
相关PDF资料 |
PDF描述 |
|---|---|
| PALCE16V8Z-12JI | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| PALCE16V8Z-12PI | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| PALCE16V8Q-20PI/4 | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| PALCE16V8H-25PI/4 | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| PALCE16V8Q-25PI/4 | KPT 5C 5#16 SKT RECP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PALCE16V8H-7PI | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20-Pin Universal Programmable Array Logic |
| PALCE16V8H-7PI4 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20-Pin Universal Programmable Array Logic |
| PALCE16V8H-7PI5 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20-Pin Universal Programmable Array Logic |
| PALCE16V8H-7SC | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:EE CMOS 20-Pin Universal Programmable Array Logic |
| PALCE16V8H-7SC/5 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
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