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参数资料
| 型号： | PALCE16V8Z-25SI |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| 中文描述： | EE PLD, 25 ns, PDSO20 |
| 封装： | PLASTIC, SO-20 |
| 文件页数： | 8/32页 |
| 文件大小： | 635K |
| 代理商： | PALCE16V8Z-25SI |
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16
PALCE16V8Q-10 (Com’l)
USE
GAL
DEVICES
FOR
NEW
DESIGNS
CAPACITANCE1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are dened under best case conditions. Future process improvements
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modied where
frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25 °C,
5
pF
COUT
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8
pF
Parameter
Symbol
Parameter Description
-10
Unit
Min 2
Max
tPD
Input or Feedback to Combinatorial Output
3
10
ns
tS
Setup Time from Input or Feedback to Clock
7.5
ns
tH
Hold Time
0ns
tCO
Clock to Output
3
7.5
ns
tWL
Clock Width
LOW
6
ns
tWH
HIGH
6
ns
fMAX
Maximum Frequency
(Note 3)
External Feedback
1/(tS+tCO)
66.7
MHz
Internal Feedback (fCNT)
1/(tS+tCF) (Note 4)
71.4
MHz
No Feedback
1/(tWH+tWL)
83.3
MHz
tPZX
OE to Output Enable
210
ns
tPXZ
OE to Output Disable
210
ns
tEA
Input to Output Enable Using Product Term Control
3
10
ns
tER
Input to Output Disable Using Product Term Control
3
10
ns
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