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参数资料
| 型号： | PALCE22V10Z-25SI |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | Hook-Up Wire; Conductor Size AWG:18; No. Strands x Strand Size:19 x 30; Jacket Color:Yellow; Approval Bodies:UL; Approval Categories:UL AWM Style 1180; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/5 Type EE RoHS Compliant: Yes |
| 中文描述： | EE PLD, 25 ns, PDSO24 |
| 封装： | PLASTIC, SOIC-24 |
| 文件页数： | 23/34页 |
| 文件大小： | 691K |
| 代理商： | PALCE22V10Z-25SI |
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PALCE22V10 and PALCE22V10Z Families
3
Variable Input/Output Pin Ratio
The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin.
Buffers for device inputs have complementary outputs to provide user-programmable input signal
polarity. Unused input pins should be tied to VCC or GND.
Registered Output Conguration
Each macrocell of the PALCE22V10 includes a D-type ip-op for data storage and
synchronization. The ip-op is loaded on the LOW-to-HIGH transition of the clock input. In the
registered conguration (S1 = 0), the array feedback is from Q of the ip-op.
Combinatorial I/O Conguration
Any macrocell can be congured as combinatorial by selecting the multiplexer path that bypasses
the ip-op (S1 = 1). In the combinatorial conguration, the feedback is from the pin.
0 = Programmed EE bit
1 = Erased (charged) EE bit
Figure 1. Output Logic Macrocell Diagram
16564E-004
CLK
S1
10
11
00
01
AR
SP
0
1
I/On
S0
D Q
Q
S1
S0
Output Conguration
0
Registered/Active Low
0
1
Registered/Active High
1
0
Combinatorial/Active Low
1
Combinatorial/Active High
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| PALCE24V10H15JC | 制造商:AMD 功能描述:* |
| PALCE24V10H-15JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALCE24V10H-15PC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALCE24V10H25JC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:IC-SM CMOS EEPLD |
| PALCE24V10H-25JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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