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参数资料
| 型号： | PALLV22V10-15PC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | Header Connector,PCB Mnt,RECEPT,5 Contacts,PIN,0.1 Pitch,PC TAIL Terminal,LOCKING MECH |
| 中文描述： | EE PLD, 15 ns, PDIP24 |
| 封装： | 0.300 INCH, SKINNY, PLASTIC, DIP-24 |
| 文件页数： | 8/19页 |
| 文件大小： | 380K |
| 代理商： | PALLV22V10-15PC |
16
PALLV22V10 and PALLV22V10Z Families
USE
GAL
DEVICES
FOR
NEW
DESIGNS
POWER-UP RESET
The power-up reset feature ensures that all ip-ops will be reset to LOW after the device has been
powered up. The output state will depend on the programmed pattern. This feature is valuable in
simplifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise
to its steady state, two conditions are required to ensure a valid power-up reset. These conditions
are:
x
The VCC rise must be monotonic.
x
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter
Symbol
Parameter Description
Max
Unit
tPR
Power-Up Reset Time
1000
ns
tS
Input or Feedback Setup Time
See Switching
Characteristics
tWL
Clock Width LOW
tPR
tWL
tS
2.7 V
VCC
Power
Registered
Active-Low
Output
Clock
Figure 3. Power-Up Reset Waveform
18956D-018
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PALLV22V10-7JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALLV22V10Z-25JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALLV22V10Z-25PI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| PALLV22V10Z25SI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| PALM-L1 | 制造商:Panduit Corp 功能描述:B-ID |
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