参数资料
型号: PBL386612QNS
厂商: ERICSSON
英文描述: Subscriber Line Interface Circuit
中文描述: 用户线接口电路
文件页数: 14/18页
文件大小: 115K
代理商: PBL386612QNS
PBL 386 61/2
14
Preliminary
RESISTORS: (Values according to IEC-63 E96
series)
R
SG
R
LD
R
LC
R
REF
R
T
R
TX
R
B
R
RX
R
FB
R
1
R
2
R
3
R
4
R
RT
R
RF
R
F1
, R
F2
= 23.7 k
= 49.9 k
= 18.7 k
= 15 k
= 105 k
= 32.4k
= 57.6k
= 105k
Depending on CODEC / filter
= 604 k
1%
1
/
10
W
= 604 k
1%
1
/
10
W
= 249 k
1%
1
/
10
W
= 280 k
1%
1
/
W
= 332
5% 2 W
= 332
5% 2 W
= Line resistor, 40
1%
1%
1
/
10
W
1%
1
/
10
W
1%
1
/
10
W
1%
1
/
10
W
1%
1
/
10
W
1%
1
/
10
W
1%
1
/
10
W
1%
1
/
W
CAPACITORS:(Values according to IEC-63 E6
series)
C
B
C
B2
C
VCC
C
VEE
C
TC
C
RC
C
HP
C
LP
C
GG
C
1
C
2
= 100 nF
= 150 nF
= 100 nF
= 100 nF
= optional
= optional
= 68 nF
= 330 nF
= 220 nF
= 330 nF
= 330 nF
100 V 20%
100 V 20%
10 V 20%
10 V* 20%
100 V 20%
100 V 20%
100 V 20%
63 V 10%
63 V 10%
*100V if VEE pin connected to VBAT, VBAT2
DIODES:
Figure 12. Single-channel subscriber line interface with PBL 386 61/2 and combination CODEC/filter
D
B
D
B2
D
BB
= 1N4448
= 1N4448
= 1N4448 (optional)
OVP:
Secondary protection (eg Power Innovations TISP
PBL1 or PBL2). The ground terminals of the
secondary protection should be connected to the
common ground on the Printed Board Assembly
with a track as short and wide as possible,
preferably a groundplane.
C
VCC
CODEC/
Filter
SYSTEM CONTROL
INTERFACE
D
B2
C
RC
C
LP
C
HP
TIP
RING
OVP
+12 V /+5V
C
1
R
4
E
RG
R
RT
R
T
KR
VB
VB2
VCC
VCC
C
GG
C
2
R
3
C
TC
D
B
VEE
VEE
BGND
TIPX
VBAT
VBAT2
C1
C2
C3
VCC
AOV
PSG
LP
DR
PLD
PLC
NC
REF
TS
NC
HP
RINGX
AGND
RSN
DET
NC
RRLY
VTX
DT
VEE
R
FB
R
RX
R
B
R
LD
R
LC
R
REF
R
F1
R
F2
R
1
R
2
R
SG
D
BB
C
B2
PBL 386 61/2
VB
R
TX
VBAT<VEE<-5 V
out
-
+
out
C
VEE
R
RF
+5 V
C
B
tip and ring.
The ring trip function is based on a polar-
ity change at the comparator input when
the line goes off-hook. In the on-hook state
no dc current flows through the loop and
the voltage at comparator input DT is more
positive than the voltage at input DR. When
the line goes off-hook, while the ring relay
is energized, dc current flows and the com-
parator input voltage reverses polarity.
Figure 12 gives an example of a ring trip
detection network. This network is applica-
ble, when the ring voltage superimposed
on the battery voltage is injected on the ring
lead of the two-wire port. The dc voltage
across sense resistor R
is monitored by
the ring trip comparator input DT and DR
via the filter network R
, R
, R
, R
, C
and
C
. DT is more positive than DR, with the
line on-hook (no dc current). The DET
output will report logic level high, i.e. the
detector is not tripped. When the line goes
off-hook, while ringing, a dc current will flow
through the loop including sense resistor
R
and will cause the input DT to become
more negative than input DR. This chang-
es the output on the DET pin to logic level
low, i.e. tripped detector condition. The
system controller (or line card processor)
responds by de-energizing the ring relay
via the SLIC, i.e. ring trip.
Complete filtering of the 20 Hz ac compo-
nent at terminals DT and DR is not neces-
sary. A toggling DET output can be exam-
ined by a software routine to determine the
duty cycle. Off-hook condition is indicated
when the DET output is at logic level low for
more than half the time.
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