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参数资料
| 型号： | PBL38665-2 |
| 厂商： | ERICSSON |
| 英文描述： | Subscriber Line Interface Circuit |
| 中文描述： | 用户线接口电路 |
| 文件页数： | 8/18页 |
| 文件大小： | 184K |
| 代理商： | PBL38665-2 |
PBL 386 65/2
8
Preliminary
Pin Description
Refer to figure 8.
PLCC SSOP
1
2
Symbol
VBAT
VBAT2
Description
Battery supply voltage. Negative with respect to BGND.
An optional second battery voltage, connected in series with a diode, or an external powerhandling
resistor connects to this pin.
A
daptive
O
verhead
V
oltage. If the pin is left open, then the overhead voltage is set internally to 3.1V
Peak
in off-hook and 1.4 V
in on-hook. The overhead voltage will automatically adapt to signals > 3.1V
.
If the pin is connected to AGND, then no overhead voltage is set internally. The overhead voltage adapts
automatically to 0.6 V
Peak
< signals < 6.2 V
Peak
.
P
rogrammable
S
aturation
G
uard. The resistive part of the DC feed characteristic is programmed by a
resistor connected from this pin to VBAT.
L
ow
P
ass filter. Saturation guard filter capacitor connected here to filter out noise and improve PSRR.
Other end of C
LP
connects to VBAT.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level
low, indicating off-hook condition. The ring trip network connects to this input.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The ring trip network connects to this input.
-5V to VBAT power supply.
A 15 k
resistor should be connected between this pin and AGND.
S
ilent
P
olarity
R
eversal. The polarity reversal time can be adjusted with a capacitor connected to AGND.
If pin is left open: Shortest polarity reversal time.
P
rog.
L
ine
C
urrent, the constant current part of the DC feed characteristic is programmed by a resistor
connected from this pin to AGND.
P
rogrammable
L
oop
D
etector threshold. The loop detection threshold is programmed by a resistor
connected from this pin to AGND.
+5 V power supply.
C1, C2 and C3 are digital inputs
C
ontrolling the SLIC operating states. Refer to section
Operating states for details.
7
8
3
9
AOV
4
10
PSG
5
11
LP
6
12
DT
7
13
DR
8
9
10
16
17
18
VEE
REF
SPR
11
19
PLC
12
20
PLD
13
14
15
16
17
18
21
22
23
24
14
25
VCC
C3
C2
C1
NC
DET
N
o
C
onnect. Must be left open.
Det
ector output. Active low when indicating loop or ring trip detection, active high when indicating ground
key detection
R
eceive
S
umming
N
ode. 400 times the current flowing into this pin equals the metallic (transversal)
current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain
connect to the receive summing node.
A
nalog
G
rou
nd
, should be tied together with BGND.
Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of -0.5. The two-wire
impedance programming network connects between VTX and RSN.
R
ing
R
e
l
a
y
driver output.
T
ip
S
ense should be connected to TIPX.
N
o
C
onnect. Must be left open.
H
igh
P
ass connection for ac/dc separation capacitor C
HP
. Other end of C
HP
connects to RINGX.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
B
attery
G
rou
nd
, should be tied together with AGND.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
19
26
RSN
20
21
27
28
AGND
VTX
22
23
24
25
26
1
2
RRLY
TS
NC
HP
RINGX
15
3
4
27
28
5
6
BGND
TIPX
}
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相关代理商/技术参数 |
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| PBL386652QNS | 制造商:ERICSSON 制造商全称:Ericsson 功能描述:Subscriber Line Interface Circuit |
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