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参数资料
| 型号： | PC100-222-620 |
| 厂商： | SIEMENS AG |
| 英文描述： | KPT 3C 3#20 SKT PLUG |
| 中文描述： | 3.3 2米x 64/72-Bit一银行内存模块3.3 4米× 64/72-Bit 2银行内存模块 |
| 文件页数： | 13/17页 |
| 文件大小： | 104K |
| 代理商： | PC100-222-620 |
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
Semiconductor Group
13
SPD-Table:
Byte#
Description
SPD Entry Value
Hex
2Mx64
-8-3
80
08
04
0B
09
2Mx72
-8-3
80
08
04
0B
09
4Mx64
-8-3
80
08
04
0B
09
4Mx72
-8-3
80
08
04
0B
09
0
1
2
3
4
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses
(for x8 SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
128
256
SDRAM
11
9
5
6
7
8
9
10
11
12
1 / 2
64 / 72
0
LVTTL
10.0 ns
6.0 ns
none / ECC
Self-Refresh,
15.6
μ
s
x8
n/a / x8
t
ccd
= 1 CLK
01
40
00
01
A0
60
00
80
01
48
00
01
A0
60
02
80
02
40
00
01
A0
60
00
80
02
48
00
01
A0
60
02
80
13
14
15
SDRAM width, Primary
Error Checking SDRAM data width
Minimum clock delay for back-to-back ran-
dom column address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module attributes
08
00
01
08
08
01
08
00
01
08
08
01
16
17
18
19
20
21
1, 2, 4, 8 & full page
2
CAS lat. = 2 & 3
CS latency = 0
Write latency = 0
non buffered/non
reg.
Vcc tol +/- 10%
10.0 ns
7.0 ns
not supported
not supported
8F
02
06
01
01
00
8F
02
06
01
01
00
8F
02
06
01
01
00
8F
02
06
01
01
00
22
23
24
25
26
SDRAM Device Attributes :General
Min. Clock Cycle Time at CAS Latency = 2
Max. data access time from Clock for CL=2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at
CL=1
Minimum Row Precharge Time
Minimum Row Active to Row Active delay
tRRD
06
A0
70
FF
FF
06
A0
70
FF
FF
06
A0
70
FF
FF
06
A0
70
FF
FF
27
28
30 ns
20 ns
1E
14
1E
14
1E
14
1E
14
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相关代理商/技术参数 |
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