- 您现在的位置：买卖IC网 > PDF目录69042 > PC13892VKR2 (FREESCALE SEMICONDUCTOR INC) 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 PDF资料下载
参数资料
| 型号： | PC13892VKR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MO-195AD, BGA-139 |
| 文件页数： | 32/75页 |
| 文件大小： | 3848K |
| 代理商： | PC13892VKR2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页当前第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页
Analog Integrated Circuit Device Data
38
Freescale Semiconductor
13892
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.
TIMING DIAGRAMS
timing requirements. The SPI input and output levels are set
independently via the SPIVCC pin by connecting it to the
desired supply. This would typically be tied to SW4
programmed for 1.80 V. The strength of the MISO driver is
programmable through the SPIDRV[1:0] bits.
Figure 5. Timing Requirements
Table 7. Timing Parameter Description
PARAMETER
DESCRIPTION
T MIN (NS)
tSELSU
Time CS has to be high before the first rising edge of CLK
15
tSELHID
Time CS has to remain high after the last falling edge of CLK
15
tSELLOW
Time CS has to remain low between two transfers
15
tCLKPER
Clock period of CLK
38
tCLKHIGH
Part of the clock period where CLK has to remain high
15
tCLKLOW
Part of the clock period where CLK has to remain low
15
tWRTSU
Time MOSI has to be stable before the next rising edge of CLK
4.0
tWRTHLD
Time MOSI has to remain stable after the rising edge of CLK
4.0
tRDSU
Time MISO will be stable before the next rising edge of CLK
4.0
tRDHLD
Time MISO will remain stable after the falling edge of CLK
4.0
tRDEN
Time MISO needs to become active after the rising edge of CS
4.0
tRDDIS
Time MISO needs to become inactive after the falling edge of CS
4.0
Notes
41.
This table reflects a maximum SPI clock frequency of 26 MHz. Slew rate for SPI MISO output driver is programmable from 0.16 to
0.66 V/ns
CS
CLK
MOSI
MISO
TSELSU
TWRTSU
TRDEN
TWRTHLD
TRDSU
TCLKPER
TCLKHIGH
TCLKLOW
TRDHLD
TSELHLD
TSELLOW
TRDDIS
相关PDF资料 |
PDF描述 |
|---|---|
| PC13892VK | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 |
| PC13892JVLR2 | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA186 |
| PC13892VL | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA186 |
| PC13892JVKR2 | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 |
| PC13892VLR2 | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA186 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PC13892VL | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC12X12 - Bulk |
| PC13892VL/R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Power Management and User Interface IC |
| PC13933A | 制造商:Thomas & Betts 功能描述:MTG FLNGE, 400A MXGRD M.I. |
| PC13CSL | 制造商:Porter Cable 功能描述:13 Amp 7 1/4" Laser Circular Saw 制造商:PORTER-CABLE 功能描述:13 AMP CIRCULAR SAW |
| PC13P11A10 | 制造商:WINCHESTER 制造商全称:Winchester Electronics Corporation 功能描述:POWER CONNECTOR CODE ORDER CHART |
发布紧急采购，3分钟左右您将得到回复。