参数资料
型号: PC28F256J3C-125
厂商: INTEL CORP
元件分类: PROM
英文描述: Intel StrataFlash Memory (J3)
中文描述: 16M X 16 FLASH 2.7V PROM, 125 ns, PBGA64
封装: LEAD FREE, BGA-64
文件页数: 55/72页
文件大小: 905K
代理商: PC28F256J3C-125
256-Mbit J3 (x8/x16)
Datasheet
55
A.5
System Interface Information
The following device information can optimize system interface software.
A.6
Device Geometry Definition
This field provides critical details of the flash device geometry.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
18:
19:
1A:
--00
--00
--00
19h
2
Table 27. CFI Identification (Sheet 2 of 2)
Offset
Length
Description
Add.
Hex
Code
Value
Table 28. System Interface Information
Offset
Length
Description
Add.
Hex
Code
Value
1Bh
1
V
logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
V
logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
V
PP
[programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
V
[programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
“n” such that typical single word program time-out = 2
n
μs
“n” such that typical max. buffer write time-out = 2
n
μs
“n” such that typical block erase time-out = 2
n
ms
“n” such that typical full chip erase time-out = 2
n
ms
“n” such that maximum word program time-out = 2
n
times
typical
“n” such that maximum buffer write time-out = 2
n
times typical
“n” such that maximum block erase time-out = 2
n
times typical
“n” such that maximum chip erase time-out = 2
n
times typical
1B:
--27
2.7 V
1Ch
1
1C:
--36
3.6 V
1Dh
1
1D:
--00
0.0 V
1Eh
1
1E:
--00
0.0 V
1Fh
20h
21h
22h
1
1
1
1
1F:
20:
21:
22:
--08
--08
--0A
--00
256 μs
256 μs
1 s
NA
23h
1
23:
--04
2 ms
24h
25h
26h
1
1
1
24:
25:
26:
--04
--04
--00
2 ms
16 s
NA
Table 29. Device Geometry Definition (Sheet 1 of 2)
Offset
Length
Description
Code See Table
Below
27:
27h
1
“n” such that device size = 2
n
in number of bytes
28h
2
Flash device interface: x8 async x16 async x8/x16 async
28:
--02
x8/
x16
28:00,29:00 28:01,29:00 28:02,29:00
“n” such that maximum number of bytes in write buffer = 2
n
29:
2A:
2B:
--00
--05
--00
2Ah
2
32
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