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参数资料
| 型号： | PC33701DWBR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 稳压器 |
| 英文描述： | 3 A SWITCHING REGULATOR, 400 kHz SWITCHING FREQ-MAX, PDSO32 |
| 封装： | PLASTIC, SOIC-32 |
| 文件页数： | 3/24页 |
| 文件大小： | 841K |
| 代理商： | PC33701DWBR2 |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33701
11
Timing Diagram
Figure 2. Definition of Time on the I2C Bus
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical
application circuit (see Figure 20) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LINEAR REGULATOR (LDO)
LDO Output Current Slew Rate
ISR
–
TBD
–
mA/
s
Fault Condition Timeout
tFAULT
–1.0–
ms
Retry Timer Cycle
tRet
–
100
–
ms
SCA, SCL PIN, I2C BUS (STANDARD)
SCL Clock Frequency
fSCL
0
–
100
kHz
Bus Free Time Between a STOP and a START Condition
tBUF
4.7
–
s
Hold Time (Repeated) START Condition (After this period, the first clock pulse
is generated.)
tHD-STA
4.0
–
s
Low Period of the SCL Clock
tLOW
4.7
–
s
High Period of the SCL Clock
tHIGH
4.0
–
s
SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to 400 pF,
3.0 mA Sink Current
tF
–
250
ns
Setup Time for a Repeated START Condition
tSU-STA
4.7
–
s
tHD-DAT
0––
s
Data Setup Time
tSU-DAT
250
–
ns
Setup Time for STOP Condition
tSU-STO
4.0
–
s
Capacitive Load for Each Bus Line
CB
–
400
pF
Notes
10.
Design Information only. Not production tested.
11.
The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
tSU-STO
tSU-STA
tHD-STA
tSU-DAT
tHD-DAT
tHD-STA
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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