参数资料
型号: PC33702DWB
厂商: MOTOROLA INC
元件分类: 稳压器
英文描述: 3.0 A Switch-Mode Power Supply with Linear Regulator
中文描述: 6 A SWITCHING REGULATOR, 400 kHz SWITCHING FREQ-MAX, PDSO32
封装: PLASTIC, SOIC-32
文件页数: 11/24页
文件大小: 841K
代理商: PC33702DWB
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
11
Timing Diagram
Figure 2. Definition of Time on the I
2
C Bus
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C
T
J
125
°
C unless otherwise noted. Input voltages V
IN1
= V
IN2
= 3.3 V using the typical
application circuit (see
Figure 20
) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LINEAR REGULATOR (L
DO
)
LDO Output Current Slew Rate
I
SR
TBD
mA/
μ
s
Fault Condition Timeout
t
FAULT
1.0
ms
Retry Timer Cycle
t
R
et
100
ms
SCA, SCL PIN, I
2
C BUS (STANDARD)
SCL Clock Frequency
f
SCL
0
100
kHz
Bus Free Time Between a STOP and a START Condition
t
BUF
4.7
μ
s
Hold Time (Repeated) START Condition (After this period, the first clock pulse
is generated.)
t
HD-STA
4.0
μ
s
Low Period of the SCL Clock
t
LOW
4.7
μ
s
High Period of the SCL Clock
t
HIGH
4.0
μ
s
SDA Fall Time from V
IH_MAX
to V
IL_MIN
, Bus Capacitance 10 pF to 400 pF,
3.0 mA Sink Current
t
F
250
ns
Setup Time for a Repeated START Condition
t
SU-STA
4.7
μ
s
Data Hold Time for I
2
C bus devices
(Note 10)
,
(Note 11)
t
HD-DAT
0
μ
s
Data Setup Time
t
SU-DAT
250
ns
Setup Time for STOP Condition
t
SU-STO
4.0
μ
s
Capacitive Load for Each Bus Line
C
B
400
pF
Notes
10.
11.
Design Information only. Not production tested.
The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the V
IH_MIN
of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
t
SU-STO
t
SU-STA
t
HD-STA
t
SU-DAT
t
HD-DAT
t
HD-STA
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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