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参数资料
| 型号： | PC33880DWR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSH DC MOTOR CONTROLLER, 2 A, PDSO28 |
| 封装： | PLASTIC, SOIC-28 |
| 文件页数： | 3/24页 |
| 文件大小： | 362K |
| 代理商： | PC33880DWR2 |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880
11
Figure 2. SPI Timing Diagram
Digital Interface Timing
Recommended Frequency of SPI Operation
—
4.0
6.0
MHz
tRESET
—4.0
10
s
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
tLEAD
100
—
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
tLAG
50
—
ns
DI to Falling Edge of SCLK (Required Setup Time)
tDI(su)
16
—
ns
Falling Edge of SCLK to DI (Required Hold Time)
tDI(HOLD)20
—
ns
DI, CS, SCLK Signal Rise Time (Note17)
tr(DI)
—5
—
ns
DI, CS, SCLK Signal Fall Time (Note17)
tf(DI)
—5
—
ns
Time from Falling Edge of CS to DO Low Impedance (Note18)
tDO(EN)
—
55
ns
Time from Rising Edge of CS to DO High Impedance (Note19)
tDO(DIS)
—
55
ns
Time from Rising Edge of SCLK to DO Data Valid (Note20)
tVALID
—25
55
ns
Notes:
16.
This parameter is guaranteed by design, but not production tested.
17.
Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
18.
Time required for output status data to be available for use at DO pin.
19.
Time required for output status data to be terminated at DO pin
20.
Time required to obtain valid data out from DO following the rise of SCLK.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 4.75 V
≤ V
DD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted. Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C
Characteristic
Symbol
Min
Typ
Max
Units
tDO(dis)
0.7 VDD
0.2 VDD
0.7 VDD
0.2 VDD
tlead
tDO(en)
tDI(su)
tDI(hold)
tvalid
tlag
CS
SCLK
DI
DO
MSB in
MSB out
LSB out
0.7 VDD
0.2 VDD
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