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参数资料
| 型号： | PC33889DW |
| 厂商： | MOTOROLA INC |
| 元件分类： | 网络接口 |
| 英文描述： | System Basis Chip Lite with Low Speed Fault Tolerant CAN Interface |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDSO28 |
| 封装： | PLASTIC, SO-28 |
| 文件页数： | 13/30页 |
| 文件大小： | 464K |
| 代理商： | PC33889DW |
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PC33889
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PC33889
In stop mode the Software watchdog can be “running” or “not running” depending upon selection by SPI. Refer to SPI
description, RCR register bit WDSTOP. If W/D is enabled the SBC must be wake up before W/D time expired, otherwise a reset
is generated. In stop mode, SBC wake up capability are identical as in sleep mode.
4.5.4.1
Stop mode: wake up from SBC side, INT pin activation:
When application is in stop mode, it can wake up from the SBC side. When a wake up is detected by the SBC (ex CAN, Wake
up input, forced wake up etc.) the SBC turns itself into Normal request mode and activated the Vdd1 main regulator. When the
main regulator is fully active, then the wake up is signalled to the MCU through the INT pin. INT pin is pulled low for 10us and
then returns high. Wake up event can be read through the SPI registers.
4.5.4.2
Stop mode: wake up from MCU side:
When application is in stop mode, the wake up event may come to the MCU. In this case the MCU has to signal to the SBC
that it has to go into Normal mode in order for the Vdd1 regulator to be able to deliver full current capability. This is done by a low
to high transition of the CSB pin. CSB pin low to high activation has to be done as soon as possible after the MCU. The SBC
generates a pulse at INTB pin. Alternatively the L0 and L1 inputs can also be used as wake up from stop mode.
4.5.4.3
Stop mode current monitoring
If the current in stop mode exceed the Idd1s-wu threshold, the SBC jumps into Normal request mode, activated the Vdd1
main regulator and generate and interrupt to the MCU. This interrupt is not maskable and not bit are set into the INT register.
4.5.4.4
Software watchdog in stop mode:
If watchdog is enabled (register MCR, bit WDSTOP set), the MCU has to wake up independently of the SBC before the end
of the SBC watchdog time. In order to do this the MCU has to signal the wake to the SBC through the SPI wake up (CSB pin low
to high transition to activated SPI wake up). Then the SBC wakes up and jump into the normal request mode. MCU has to
configure the SBC to go to either normal or standby mode. The MCU can then decide to go back again to stop mode.
If no MCU wakes up occurs within the watchdog timing, the SBC will activate the reset pin and jump into the normal request
mode. The MCU can then be initialized.
4.5.5
Normal request mode:
This is a temporary mode automatically accessed by the device after a wake up event from sleep or stop mode or after
device power up. In this mode the Vdd1 regulator is ON, V2 is off, the reset pin is high. As soon as the device enters the normal
request mode an internal 350ms timer is started. During these 350ms the micro controller of the application must addressed the
SBC via SPI and configure the watchdog register (TIM1 register). This is the condition for the SBC to leave the Normal request
Mode and enter the Normal mode and to set the watchdog timer according to configuration done during the Normal Request
mode.
“BATFAIL flag” is a bit which is triggered when Vsup is below 3V. This bit is set into the MCR register. It is reset by MCR
register read.
4.6
Internal Clock
The device has an internal clock used to generate all timings (reset, watchdog, cyclic wake up, filtering time etc....).
4.7
Reset pin
A reset output is available in order to reset the microcontroller. The reset cause are:
- Vdd1 falling out of range: if Vdd1 fall below the reset threshold (parameter
Rst-th
), the reset pin is pull low until Vdd1 return
to nominal voltage.
- Power on reset: at device power on or at device wake up from sleep mode, the reset is maintained low until Vdd1 is within
its operation range.
- Watchdog time out: if the watchdog is not cleared the SBC will pull the reset pin low for the duration of the reset duration
time
(
parameter: reset-dur).
For debug purposes at 25°C, reset pin can be shorted to 5V.
4.8
Software watchdog (selectable window or time out watchdog)
Software watchdog is used in the SBC normal and stand-by modes for the MCU monitoring. The watchdog can be either
window or time out. This is selectable by SPI (register TIM, bit WDW). Default is window watchdog. The period for the watchdog
is selectable by SPI from 5 to 350ms (register TIM, bits WDT0 and WDT1). When the window watchdog is selected, the closed
window is the first half of the selected period, and the open window is the second half of the period. The watchdog can only be
cleared within the open window time. An attempt to clear the watchdog in the closed window will generate a reset. Watchdog is
cleared through SPI by addressing the TIM register.
Refer to” table for reset pin operations operation in mode 2.
4.9
Wake Up capabilities
Several wake-up capabilities are available for the device when it is in sleep or stop mode. When a wake up has occurred, the
wake up event is stored into the WUR or CAN registers. The MCU can then access to the wake up source. The wake up options
are selectable trough SPI while the device is in normal or standby mode and prior to go to enter low power mode (sleep or stop
mode).
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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.
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