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参数资料
| 型号： | PC33999EK |
| 厂商： | Motorola, Inc. |
| 英文描述： | 16-Output Switch with SPI and PWM Control |
| 中文描述： | 16 - SPI和输出的PWM控制开关 |
| 文件页数： | 7/16页 |
| 文件大小： | 627K |
| 代理商： | PC33999EK |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33999
7
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 3.1 V
≤
SO
PWR
≤
5.25 V, 9.0 V
≤
V
PWR
≤
16 V, -40°C
≤
T
C
≤
125°C, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with V
PWR
= 13 V, T
A
= 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate
R
L
= 56
(Note 16)
SR
1.0
2.0
10
V/
μ
s
Output Turn ON Delay Time (Note 17)
t
DLY
(
on
)
1.0
15
50
μ
s
Output Turn OFF Delay Time (Note 17)
t
DLY
(
off
)
1.0
15
50
μ
s
Output ON Short Fault Disable Report Delay (Note 18)
t
DLY
(
short
)
100
–
450
μ
s
Output OFF Open Fault Delay Time (Note 18)
t
DLY
(
open
)
100
–
450
μ
s
Output PWM Frequency
t
FREQ
–
–
2.0
kHz
DIGITAL INTERFACE TIMING
Required Low State Duration on V
PWR
for Reset
V
PWR
≤
0.2 V (Note 19)
t
RST
–
–
10
μ
s
Falling Edge of
CS
to Rising Edge of SCLK (Required Setup Time)
t
LEAD
100
–
–
ns
Falling Edge of SCLK to Rising Edge of
CS
(Required Setup Time)
t
LAG
50
–
–
ns
SI to Falling Edge of SCLK (Required Setup Time)
t
SI(
su
)
16
–
–
ns
Falling Edge of SCLK to SI (Required Setup Time)
t
SI(
hold
)
20
–
–
ns
SI,
CS
, SCLK Signal Rise Time (Note 20)
t
r(SI)
–
5.0
–
ns
SI,
CS
, SCLK Signal Fall Time (Note 20)
t
f(SI)
–
5.0
–
ns
Time from Falling Edge of
CS
to SO Low Impedance (Note 21)
t
SO(
en
)
–
–
50
ns
Time from Rising Edge of
CS
to SO High Impedance (Note 22)
t
SO(
dis
)
–
–
50
ns
Time from Rising Edge of SCLK to SO Data Valid (Note 23)
t
VALID
–
25
80
ns
Notes
16.
17.
18.
19.
20.
21.
22.
23.
Output slew rate measured across a 56
resistive load.
Output turn ON and OFF delay time measured from 50% rising edge of CS to 90% and 10% of initial voltage.
Duration of fault before fault bit is set. Duration between access times must be greater than 450
μ
s to read faults.
This parameter is guaranteed by design but is not production tested.
Rise and Fall time of incoming SI,
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output status data to be terminated at SO pin.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PC33999EK/R2 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:16-Output Switch with SPI and PWM Control |
| PC33B | 制造商:Datak Corporation 功能描述: |
| PC33P11A10 | 制造商:WINCHESTER 制造商全称:Winchester Electronics Corporation 功能描述:POWER CONNECTOR CODE ORDER CHART |
| PC33P11A11 | 制造商:WINCHESTER 制造商全称:Winchester Electronics Corporation 功能描述:POWER CONNECTOR CODE ORDER CHART |
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