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参数资料
| 型号： | PC34710EWR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 稳压器 |
| 英文描述： | Adjustable Dual Output Switching Power Supply |
| 中文描述： | 1.2 A SWITCHING REGULATOR, 260 kHz SWITCHING FREQ-MAX, PDSO32 |
| 封装： | LEAD FREE, PLASTIC, SOIC-32 |
| 文件页数： | 10/16页 |
| 文件大小： | 518K |
| 代理商： | PC34710EWR2 |
34710
10
Go to: www.freescale.com
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
V
I/O
Switching Regulator
The V
I/O
switching regulator output voltage is determined by
the MODE digital input terminals. The 34710’s MODE[2:0]
select the output voltage (
Table 1
). For example, if
MODE[2:0] = 0, 0, 0, then V
I/O
= 5.0 V; if MODE[2:0] = Open,
Open, Open, then V
I/O
= 3.3 V. The MODE0 terminal controls
the output voltage of both regulators.
The topology of the regulator is a bang-bang buck regulator
operating from the internal ~200 kHz oscillator.
V
CORE
Linear Regulator
The V
CORE
linear regulator can produce a +3.3 V, 2.5 V,
1.8 V, or 1.5 V output voltage at 500 mA. The input to the
V
CORE
regulator is a terminal that may be connected to the V
I/
O
regulator output. The minimum input voltage must be
V
CORE
(
NOM
) + 0.8 V.
The MODE[2:0] terminals select the output voltage as
depicted in
Table 1
.
SUPERVISORY AND MISCELLANEOUS FUNCTIONS
Introduction
The supervisor circuitry provides control of the
RST
line, an
open drain signal, based on system operating conditions
monitored by the 34710. V
I/O
, V
CORE
, V
B+
, and thermal
shutdown (TSD) detectors in various parts of the chip are
monitored for error conditions. Because other devices in the
system may trigger a reset, the
RST
line itself is also monitored,
but the supervisor circuitry controls all reset timing, including
externally generated resets. Driving the
RST
line low causes the
system to be held in the reset state. V
I/O
, V
CORE
, V
B+
, and
thermal shutdown have both positive- and negative-going
thresholds.
The supervisor circuitry also ensures that the power supplies
sequence properly. Specifically, that V
I/O
is never less than
TBD V below V
CORE
. This means that V
CORE
-
V
I/O
will be
clamped at 0.5 V, and that the V
CORE
regulator operation will be
suppressed during startup and shutdown to ensure that
V
CORE
-
V
I/O
= TBD V.
Static Operating Specifications
The
RST
output is an I/O device with an open drain output
driver with a pullup and a CMOS digital input gate (
Figure 3
).
This I/O structure allows wired OR connection to the MCU’s
RST
I/O terminal, as well as allowing the MCU to initiate a reset
cycle by driving its
RST
terminal low.
When responding to a
MCU request for a reset cycle, the 34710 must respond rapidly
enough to prevent a glitch.
Figure 2
, page 9, shows the timing
parameters for responding to an externally applied
RST
signal.
The rise time may be relatively slow, depending on the load
capacitance, and the internal
RST
input gate must operate
reliably (no oscillations during the transition) under these
conditions, i.e., the
RST
input can be inhibited for up to
t
phsl
(
MAX
). Error conditions must be present for a minimum
time, t
filter
, before the 34710 responds to them. Once all error
conditions are cleared,
RST
is held low for an additional time of
t
delay
. If any monitored item falls below its negative-going
threshold for t
filter
, 1.0
μ
s to 6.0
μ
s, the t
delay
will be restarted
when system operating conditions are met. The trigger for the
t
delay
retriggerable one shot should be ([V
I/O
(
LOW
) +
V
CORE
(
LOW
) + V
B+
(
LOW
) + T
J
(
TSD
)] & t
filter
), where t
filter
is the
1.0
μ
s to 6.0
μ
s delay.
Figure 3.
RST
Terminal Interface
Table 1. V
I/O
and V
CORE
(NOM)
Regulator
Output Voltage Selection
MODE2
MODE1
MODE0
V
I/O
(V)
V
CORE
(NOM)
(V)
0
0
0
5.0
3.3
0
0
Open
3.3
2.5
0
Open
0
5.0
1.8
0
Open
Open
3.3
1.8
Open
0
0
5.0
2.5
Open
0
Open
3.3
2.5
Open
Open
0
5.0
1.5
Open
Open
Open
3.3
1.5
Open indicates terminal is not connected externally.
From
Internal
Reset
Circuits
To Internal
Gates
RST
C
LOAD
(Optional)
V
I/O
R
PULLUP
≥
4.7 k
(Optional)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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