参数资料
型号: PCA24S08D/DG,118
厂商: NXP Semiconductors
文件页数: 15/25页
文件大小: 0K
描述: IC EEPROM CMOS 1024X8 8-SOIC
标准包装: 2,500
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 8K (1K x 8)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 2.5 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 带卷 (TR)
其它名称: 935287848118
NXP Semiconductors
PCA24S08
1024 × 8-bit CMOS EEPROM with access protection
9. Dynamic characteristics
Table 8. Dynamic characteristics
C L = 1 TTL gate and 100 pF, except as noted. V DD = 2.5 V to 3.6 V.
Symbol
Parameter
Conditions
Standard-mode
Fast-mode I 2 C-bus
Unit
I 2 C-bus
Min
Max
Min
Max
f SCL
t BUF
SCL clock frequency
bus free time between a STOP and
0
4.7
100
-
0
1.3
400
-
kHz
μ s
START condition
t HD;STA
t SU;STA
hold time (repeated) START condition
set-up time for a repeated START
4.0
4.7
-
-
0.6
0.6
-
-
μ s
μ s
condition
t SU;STO
t HD;DAT
set-up time for STOP condition
data hold time
4.0
0
-
-
0.6
0
-
-
μ s
ns
t VD;ACK
data valid acknowledge time
[1]
-
600
-
600
ns
t VD;DAT
t SU;DAT
t LOW
t HIGH
t f
t r
t SP
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be
LOW level
HIGH level
[2]
[2]
-
-
250
4.7
4.0
-
-
-
600
1500
-
-
-
300
1000
50
-
-
100
1.3
0.6
20 + 0.1C b
20 + 0.1C b
-
[3]
[3]
600
600
-
-
-
300
300
50
ns
ns
ns
μ s
μ s
ns
ns
ns
suppressed by the input filter
[1]
[2]
[3]
t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
t VD;DAT = minimum time for SDA data out to be valid following SCL LOW.
C b = total capacitance of one bus line in pF.
SDA
t BUF
t r
t f
t HD;STA
t SP
t LOW
SCL
t HD;STA
t SU;STA
t SU;STO
P
S
t HD;DAT
t HIGH
t SU;DAT
Sr
P
002aaa986
Fig 12. Timing diagram for serial interface
PCA24S08_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 11 May 2010
? NXP B.V. 2010. All rights reserved.
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