参数资料
型号: PCA8574N,112
厂商: NXP Semiconductors
文件页数: 32/32页
文件大小: 0K
描述: IC I/O EXPANDER I2C 8B 16DIP
标准包装: 28
接口: I²C
输入/输出数: 8
中断输出:
频率 - 时钟: 400kHz
电源电压: 2.3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 16-DIP(0.300",7.62mm)
供应商设备封装: 16-DIP
包装: 管件
包括: POR
其它名称: 568-4240-5
935283486112
PCA8574N
PCA8574_PCA8574A
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 3 June 2013
9 of 32
NXP Semiconductors
PCA8574; PCA8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Simple code WRITE mode:
<S> <slave address + write> <ACK> <data out> <ACK> <data out> <ACK> ...
<data out> <ACK> <P>
Remark: Bold type = generated by slave device.
8.3 Reading from a port (Input mode)
The port must have been previously written to logic 1, which is the condition after
power-on reset. To enter the Read mode the master (microcontroller) addresses the slave
device and sets the last bit of the address byte to logic 1 (address byte read). The slave
will acknowledge and then send the data byte to the master. The master will NACK and
then send the STOP condition or ACK and read the input register again.
The read of any pin being used as an output will indicate HIGH or LOW depending on the
actual state of the input pin.
If the data on the input port changes faster than the master can read, this data may be
lost. The DATA 2 and DATA 3 are lost because these data did not meet the setup time and
hold time (see Figure 9).
Simple code for Read mode:
<S> <slave address + read> <ACK> <data in> <ACK> ... <data in> <ACK> <data in>
<NACK> <P>
Remark: Bold type = generated by slave device.
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at
any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input
data is lost.
Fig 9.
Read mode (input)
A5 A4 A3 A2 A1 A0
1
A
SA6
slave address
START condition
R/W
acknowledge
from slave
002aah383
data from port
A
acknowledge
from master
SDA
1
no acknowledge
from master
read from
port
data at
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
tv(INT)
trst(INT)
th(D)
tsu(D)
trst(INT)
DATA 1
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