参数资料
型号: PCA9530D,112
厂商: NXP Semiconductors
文件页数: 6/24页
文件大小: 0K
描述: IC LED DRIVER RGB 8-SOIC
标准包装: 100
拓扑: 开路漏极,PWM
输出数: 2
内部驱动器:
类型 - 主要: 背光,LED 闪烁器
类型 - 次要: RGB
频率: 400kHz
电源电压: 2.3 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 管件
工作温度: -40°C ~ 85°C
其它名称: 935276296112
PCA9530D
PCA9530D-ND
NXP Semiconductors
PCA9530
2-bit I 2 C-bus LED dimmer
6.3.5 PWM1 - Pulse Width Modulation 1
The PWM1 register determines the duty cycle of BLINK1. The outputs are LOW (LED on)
when the count is less than the value in PWM1 and HIGH (LED off) when it is greater.
If PWM1 is programmed with 00h, then the PWM1 output is always HIGH (LED off).
The duty cycle of BLINK1 = PWM1 / 256.
Table 8.
PWM1 - Pulse Width Modulation 1 register description
Bit
Symbol
Default
7
PWM1
[7]
1
6
PWM1
[6]
0
5
PWM1
[5]
0
4
PWM1
[4]
0
3
PWM1
[3]
0
2
PWM1
[2]
0
1
PWM1
[1]
0
0
PWM1
[0]
0
6.3.6 LS0 - LED selector
The LS0 LED select register determines the source of the LED data.
00 = output is set high-impedance (LED off; default)
01 = output is set LOW (LED on)
10 = output blinks at PWM0 rate
11 = output blinks at PWM1 rate
Table 9. LS0 - LED selector register bit description
Legend: * default value.
Register
LS0
Bit
7:4
3:2
1:0
Value
1111*
00*
00*
Description
reserved
LED1 selected
LED0 selected
6.4 Pins used as GPIOs
LEDn pins not used to control LEDs can be used as General Purpose I/Os (GPIOs).
For use as input, set LEDn to high-impedance (00) and then read the pin state via the
INPUT register.
For use as output, connect external pull-up resistor to the pin and size it according to the
DC recommended operating characteristics. LEDn output pin is HIGH when the output is
programmed as high-impedance, and LOW when the output is programmed LOW through
the ‘LED selector’ register LS0. The output can be pulse-width controlled when PWM0 or
PWM1 are used.
6.5 Power-on reset
When power is applied to V DD , an internal Power-On Reset (POR) holds the PCA9530 in
a reset condition until V DD has reached V POR . At that point, the reset condition is released
and the PCA9530 registers are initialized to their default states, all the outputs in the
OFF state. Thereafter, V DD must be lowered below 0.2 V to reset the device.
PCA9530_3
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 26 February 2009
6 of 24
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