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| 型号： | PCA9533DP/02,118 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER RGB 8-TSSOP |
| 标准包装： | 1 |
| 拓扑： | 开路漏极，PWM |
| 输出数： | 4 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光，LED 闪烁器 |
| 类型 - 次要： | RGB |
| 频率： | 400kHz |
| 电源电压： | 2.3 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 85°C |
| 配用： | 568-4003-ND - DEMO BOARD LED DIMMER 568-3512-ND - DEMO BOARD UART TO I2C |
| 其它名称： | 568-3375-6 |
NXP Semiconductors
PCA9533
4-bit I 2 C-bus LED dimmer
11. Dynamic characteristics
Table 14.
Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode
Fast-mode I 2 C-bus
Unit
I 2 C-bus
Min
Max
Min
Max
f SCL
t BUF
SCL clock frequency
bus free time between a STOP and
0
4.7
100
-
0
1.3
400
-
kHz
μ s
START condition
t HD;STA
t SU;STA
hold time (repeated) START condition
set-up time for a repeated START
4.0
4.7
-
-
0.6
0.6
-
-
μ s
μ s
condition
t SU;STO
t HD;DAT
set-up time for STOP condition
data hold time
4.0
0
-
-
0.6
0
-
-
μ s
ns
t VD;ACK
data valid acknowledge time
[1]
-
600
-
600
ns
t VD;DAT
t SU;DAT
t LOW
t HIGH
t r
t f
t SP
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
pulse width of spikes that must be
LOW-level
HIGH-level
[2]
[2]
-
-
250
4.7
4.0
-
-
-
600
1500
-
-
-
1000
300
50
-
-
100
1.3
0.6
0.1C b [3]
20 +
0.1C b [3]
20 +
-
600
600
-
-
-
300
300
50
ns
ns
ns
μ s
μ s
ns
ns
ns
suppressed by the input ?lter
Port timing
t v(Q)
t su(D)
t h(D)
data output valid time
data input set-up time
data input hold time
-
100
1
200
-
-
-
100
1
200
-
-
ns
ns
μ s
[1]
[2]
[3]
t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
t VD;DAT = minimum time for SDA data output to be valid following SCL LOW.
C b = total capacitance of one bus line in pF.
PCA9533_3
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2009
15 of 24
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