参数资料
型号: PCA9624BS,118
厂商: NXP Semiconductors
文件页数: 13/37页
文件大小: 0K
描述: IC LED DVR 8BIT 40V HVQFN24
产品培训模块: I²C Bus Fundamentals
标准包装: 1
拓扑: 开路漏极,PWM
输出数: 8
内部驱动器:
类型 - 主要: 背光,LED 闪烁器
类型 - 次要: RGBA
频率: 100kHz ~ 1MHz
电源电压: 2.3 V ~ 5.5 V
输出电压: 40V
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-HVQFN(4x4)
包装: 标准包装
工作温度: -40°C ~ 85°C
其它名称: 568-5304-6
NXP Semiconductors
PCA9624
8-bit Fm+ I 2 C-bus 100 mA 40 V LED driver
7.4 Active LOW output enable input
The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at
the same time.
? When a LOW level is applied to OE pin, all the LED outputs are enabled.
? When a HIGH level is applied to OE pin, all the LED outputs are high-impedance.
The OE pin can be used as a synchronization signal to switch on/off several PCA9624
devices at the same time. This requires an external clock reference that provides blinking
period and the duty cycle.
The OE pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined
blinking pattern. Do not use OE as an external dimming control signal when internal global
dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined
dimming pattern.
Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated.
Consider disabling LED outputs using HIGH level applied to OE pin.
7.5 Power-on reset
When power is applied to V DD , an internal power-on reset holds the PCA9624 in a reset
condition until V DD has reached V POR . At this point, the reset condition is released and the
PCA9624 registers and I 2 C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, V DD must be lowered below
0.2 V to reset the device.
7.6 Software reset
The Software Reset Call (SWRST Call) allows all the devices in the I 2 C-bus to be reset to
the power-up state value through a specific formatted I 2 C-bus command. To be performed
correctly, it implies that the I 2 C-bus is functional and that there is no device hanging the
bus.
The SWRST Call function is defined as the following:
1. A START command is sent by the I 2 C-bus master.
2. The reserved SWRST I 2 C-bus address ‘0000 011’ with the R/W bit set to ‘0’ (write) is
sent by the I 2 C-bus master.
3. The PCA9624 device(s) acknowledge(s) after seeing the SWRST Call address
‘0000 0110’ (06h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned to
the I 2 C-bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends
2 bytes with 2 specific values (SWRST data byte 1 and byte 2):
a. Byte 1 = A5h: the PCA9624 acknowledges this value only. If byte 1 is not equal to
A5h, the PCA9624 does not acknowledge it.
PCA9624
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 September 2012
? NXP B.V. 2012. All rights reserved.
13 of 37
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