参数资料
型号: PCA9633TK,118
厂商: NXP Semiconductors
文件页数: 16/43页
文件大小: 0K
描述: IC LED DRIVER RGBA 8-HVSON
标准包装: 1
拓扑: 开路漏极,PWM
输出数: 4
内部驱动器: 两者兼有
类型 - 主要: 背光,LED 闪烁器
类型 - 次要: RGBA
频率: 25MHz
电源电压: 2.3 V ~ 5.5 V
输出电压: 5.5V
安装类型: 表面贴装
封装/外壳: 8-VFDFN 裸露焊盘
供应商设备封装: 8-HVSON
包装: 剪切带 (CT)
工作温度: -40°C ~ 85°C
配用: OM6276,598-ND - DEMO BOARD PWM LED
622-1004-ND - BOARD DEMO FOR PHILIPS PCA9633
其它名称: 568-3239-1
NXP Semiconductors
PCA9633
4-bit Fm+ I 2 C-bus LED driver
7.4 Active LOW output enable input
The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at
the same time.
This control signal is only available for the 16-pin version and does not apply to the 8-pin
or 10-pin versions.
? When a LOW level is applied to OE pin, all the LED outputs are enabled and follow the
output state de?ned in the LEDOUT register with the polarity de?ned by INVRT bit
(MODE2 register).
? When a HIGH level is applied to OE pin, all the LED outputs are programmed to the
value that is de?ned by OUTNE[1:0] in the MODE2 register.
Table 16.
LED outputs when OE = 1
OUTNE1
0
0
1
1
OUTNE0
0
1
0
1
LED outputs
0
1 if OUTDRV = 1, high-impedance if OUTDRV = 0
high-impedance
reserved
The OE pin can be used as a synchronization signal to switch on/off several PCA9633
devices at the same time. This requires an external clock reference that provides blinking
period and the duty cycle.
The OE pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an unde?ned
blinking pattern. Do not use OE as an external dimming control signal when internal global
dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an unde?ned
dimming pattern.
7.5 Power-on reset
When power is applied to V DD , an internal Power-on reset holds the PCA9633 in a reset
condition until V DD has reached V POR . At this point, the reset condition is released and the
PCA9633 registers and I 2 C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, V DD must be lowered below
0.2 V to reset the device.
PCA9633_5
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 25 July 2008
16 of 43
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