参数资料
型号: PCA9635PW/S911,118
厂商: NXP Semiconductors
文件页数: 27/35页
文件大小: 0K
描述: IC LED DRIVER RGBA 28-TSSOP
标准包装: 2,500
拓扑: 开路漏极,PWM
输出数: 16
内部驱动器:
类型 - 主要: 背光,LED 闪烁器
类型 - 次要: RGBA
频率: 100kHz ~ 1MHz
电源电压: 2.3 V ~ 5.5 V
输出电压: 5.5V
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 带卷 (TR)
工作温度: -40°C ~ 85°C
其它名称: 935285521118
PCA9635PW/S911-T
PCA9635PW/S911-T-ND
NXP Semiconductors
PCA9635
16-bit Fm+ I 2 C-bus LED driver
13. Dynamic characteristics
Table 18.
Dynamic characteristics
Symbol Parameter
Conditions
Standard-mode
Fast-mode
Fast-mode
Unit
I 2 C-bus
I 2 C-bus
Plus I 2 C-bus
Min
Max
Min
Max
Min
Max
f SCL
t BUF
SCL clock frequency
bus free time between a
[1]
0
4.7
100
-
0
1.3
400
-
0
0.5
1000
-
kHz
μ s
STOP and START condition
t HD;STA
hold time (repeated) START
4.0
-
0.6
-
0.26
-
μ s
condition
t SU;STA
set-up time for a repeated
4.7
-
0.6
-
0.26
-
μ s
START condition
t SU;STO
set-up time for STOP
4.0
-
0.6
-
0.26
-
μ s
condition
t HD;DAT
data hold time
0
-
0
-
0
-
ns
t VD;ACK
t VD;DAT
t SU;DAT
t LOW
t HIGH
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
[2]
[3]
0.3
0.3
250
4.7
4.0
3.45
3.45
-
-
-
0.1
0.1
100
1.3
0.6
0.9
0.9
-
-
-
0.05
0.05
50
0.5
0.26
0.45
0.45
-
-
-
μ s
μ s
ns
μ s
μ s
t f
fall time of both SDA and
[4][5]
-
300
20 +
0.1C b [6]
300
-
120
ns
SCL signals
t r
rise time of both SDA and
-
1000
20 + 0.1C b [6]
300
-
120
ns
SCL signals
t SP
pulse width of spikes that
[7]
-
50
-
50
-
50
ns
must be suppressed by the
input ?lter
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
t VD;DAT = minimum time for SDA data out to be valid following SCL LOW.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V IL of the SCL signal) in order to
bridge the unde?ned region of SCL’s falling edge.
The maximum t f for the SDA and SCL bus lines is speci?ed at 300 ns. The maximum fall time (t f ) for the SDA output stage is speci?ed at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum speci?ed t f .
C b = total capacitance of one bus line in pF.
Input ?lters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
PCA9635_7
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 July 2009
27 of 35
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