参数资料
型号: PCA9673PW,118
厂商: NXP Semiconductors
文件页数: 15/33页
文件大小: 0K
描述: IC I/O EXPANDER I2C 16B 24TSSOP
标准包装: 2,500
接口: I²C
输入/输出数: 16
中断输出:
频率 - 时钟: 1MHz
电源电压: 2.3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
包括: POR
其它名称: 935283558118
PCA9673PW-T
PCA9673PW-T-ND
PCA9673
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 29 September 2011
22 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset
[3]
Cb = total capacitance of one bus line in pF.
[4]
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[6]
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Rise and fall times refer to VIL and VIH.
Fig 24. I2C-bus timing diagram
002aab175
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
SCL
SDA
tHD;STA
tSU;DAT
tHD;DAT
tf
tBUF
tSU;STA
tLOW
tHIGH
tVD;ACK
tSU;STO
1 / fSCL
tr
tVD;DAT
0.3 × VDD
0.7 × VDD
0.3 × VDD
0.7 × VDD
Fig 25. Reset timing
SDA
SCL
002aac282
trst
50 %
30 %
50 %
trec(rst)
tw(rst)
RESET
P0n, P1n
output off
START
trst
ACK or read cycle
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