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参数资料
| 型号： | PCB2421T |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | PROM |
| 英文描述： | 1K dual mode serial EEPROM |
| 中文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封装： | 3.90 MM, PLASTIC, MS-012AA, SOT-96-1, SOP-8 |
| 文件页数： | 6/24页 |
| 文件大小： | 112K |
| 代理商： | PCB2421T |
1997 Apr 01
6
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
The maximum number of data bytes transferred between
START and STOP conditions during a read operation is
unlimited.
6.3.6
A
CKNOWLEDGE
The PCB2421, when addressed in DDC2B mode, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra (9th)
clock pulse which is associated with this acknowledge bit.
The PCB2421 does not generate an acknowledge if an
internal programming cycle is in progress (SDA line is left
HIGH during the 9th clock pulse). The PCB2421 generates
an acknowledge by pulling down the SDA line during the
acknowledge pulse in such a way that the SDA line is
stable LOW during the HIGH period of the acknowledge
related clock pulse. Set-up and hold times must also be
taken into account. The master receiver must signal an
end of data to the PCB2421 by
not
generating an
acknowledge bit on the last byte that has been clocked out
of the slave transmitter. In this case, the slave transmitter
PCB2421 must leave the data line HIGH to enable the
master to generate the STOP condition.
6.3.7
S
LAVE ADDRESS
After generating a START condition, the bus master
transmits the slave address (MSB first) consisting of a 7-bit
device address (1010000) for the PCB2421. The eighth bit
of the slave address determines if the master device wants
to read or write to the PCB2421 (R/W bit) (see Fig.7).
The PCB2421 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if the
slave address was true and it is not in a programming
mode.
Table 1
Slave address
6.4
Write operation
6.4.1
B
YTE WRITE
Following the START condition from the master, the
device address (7 bits), and the R/W bit (logic LOW for
write) is placed on the bus by the master transmitter. This
indicates to the addressed slave receiver that a byte with
a word address will follow after it has generated an
acknowledge bit during the ninth clock cycle. Therefore the
next byte transmitted by the master is the word address
OPERATION
SLAVE ADDRESS
R/W
Read
Write
1010000
1010000
1
0
and will be written into the address pointer of the
PCB2421. After receiving another acknowledge signal
from the PCB2421, the master device will transmit the data
word to be written into the addressed memory location.
The PCB2421 acknowledges again and the master
generates a STOP condition. This initiates the internal
write cycle, and during this time the PCB2421 will not
generate acknowledge signals.
6.4.2
P
AGE WRITE
For a page write, the write control byte, word address, and
the first data byte are transmitted to the PCB2421 in the
same way as in a single byte write. But instead of
generating a STOP condition the master transmits up to
eight data bytes to the PCB2421 which are temporarily
stored in the on-chip page buffer and will be written into the
memory after the master has transmitted a STOP
condition. After the receipt of each word, the three lower
order address pointer bits are internally incremented by
one. The higher order four bits of the word address remain
constant. A maximum of 8 bytes can be written in one
operation. As with the byte write operation, once the STOP
condition is received an internal write cycle will begin
(see Figs 5 and 8).
6.5
Acknowledge polling
Since the device will not acknowledge during a write cycle,
this can be used to determine when the cycle is complete
(this feature can be used to maximize bus throughput).
Once the STOP condition for a write command has been
issued from the master, the device initiates the internally
timed write cycle. Acknowledge (ACK) polling can be
initiated immediately. This involves the master sending a
START condition followed by the control byte for a write
command (R/W = 0). If the device is still busy with the write
cycle, then no ACK will be returned. If the cycle is
complete, then the device will return the ACK and the
master can then proceed with the next read or write
command. See Fig.9 for flow diagram.
6.6
Write protection
Pin 3 is a write protect input (WP). In the DDC1 mode, the
PCB2421 can only be read according to the DDC1
protocol, hence the WP input has no effect in this mode.
In the DDC2B mode, whenWP is connected to ground, the
entire EEPROM is write-protected, regardless of other pin
states. When connected to V
DD
, write-protection is
disabled and the EEPROM may be programmed. WP may
not be left open-circuit.
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