
1997 Dec 16
31
Philips Semiconductors
Product specication
LCD controller/driver
PCF2104x
Notes
1. LCD outputs are open-circuit; inputs at VDD or VSS; V0 =VDD; bus inactive; internal or external clock with duty cycle
50% (IDD1 only).
2. Resets all logic when VDD <VPOR.
3. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow; this current must
not exceed
±0.5 mA.
4. Tested on sample basis.
5. Resistance of output terminals (R1 to R32 and C1 to C60) with load current Iload = 150 A; VOP =VDD VLCD =9V;
outputs measured one at a time.
6. LCD outputs open-circuit.
Logic
VIL1
LOW level input voltage pins E, RS,
R/W, DB0 to DB7 and SA0
VSS
0.3VDD
V
VIH1
HIGH level input voltage pins E, RS,
R/W, DB0 to DB7 and SA0
0.7VDD
VDD
V
VIL(osc)
LOW level input voltage pin OSC
VSS
VDD 1.5
V
VIH(osc)
HIGH level input voltage pin OSC
VDD 0.1
VDD
V
Ipu
pull-up current at pins DB0 to DB7,
RS and R/W
VI =VSS
0.04
0.15
1.00
A
IOL(DB)
LOW level output current pins
DB0 to DB7
VOL = 0.4 V; VDD =5V 1.6
mA
IOH(DB)
HIGH level output current pins
DB0 to DB7
VOH =4V; VDD =5V
1.0
mA
IL1
leakage current pins OSC, E, RS,
R/W, DB0 to DB7 and SA0
VI =VDD or VSS
1
+1
A
I2C-bus
SDA, SCL
VIL2
LOW level input voltage
note 3
VSS
0.3VDD
V
VIH2
HIGH level input voltage
note 3
0.7VDD
VDD
V
IL2
leakage current
VI =VDD or VSS
1
+1
A
Ci
input capacitance
note 4
7pF
IOL(SDA)
LOW level output current (SDA)
VOL = 0.4 V; VDD =5V 3
mA
LCD outputs
RROW
row output resistance pins
R1 to R32
note 5
1.5
3
k
RCOL
column output resistance pins
C1 to C60
note 5
36
k
Vtol1
bias voltage tolerance pins
R1 to R32 and C1 to C60
note 6
±20
±130
mV
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT