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参数资料
| 型号： | PCF8522ET |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | I2C串行EEPROM的 |
| 文件页数： | 7/24页 |
| 文件大小： | 179K |
| 代理商： | PCF8522ET |
1997 Feb 13
7
Philips Semiconductors
Product specification
256 to 1024
×
8-bit CMOS EEPROMs with
I
2
C-bus interface
PCF85xxC-2 family
8
I
2
C-BUS PROTOCOL
The I
2
C-bus is for 2-way, 2-line communication between
different ICs or modules. The serial bus consists of two
bidirectional lines: one for data signals (SDA), and one for
clock signals (SCL).
Both the SDA and SCL lines must be connected to a
positive supply voltage via a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
control signals.
8.1
Bus conditions
The following bus conditions have been defined:
Bus not busy
: both data and clock lines remain HIGH.
Start data transfer
: a change in the state of the data
line, from HIGH-to-LOW, while the clock is HIGH,
defines the START condition.
Stop data transfer
: a change in the state of the data
line, from LOW-to-HIGH, while the clock is HIGH,
defines the STOP condition.
Data valid
: the state of the data line represents valid
data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.
8.2
Data transfer
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of the data
bytes, transferred between the START and STOP
conditions is limited to 7 bytes in the E/W mode and
8 bytes in the page E/W mode.
Data transfer is unlimited in the read mode.
The information is transmitted in bytes and each receiver
acknowledges with a ninth bit.
Within the I
2
C-bus specifications a low-speed mode (2 kHz
clock rate) and a high speed mode (100 kHz clock rate)
are defined. The PCF85xxC-2 operates in both modes.
By definition a device that sends a signal is called a
‘transmitter’, and the device which receives the signal is
called a ‘receiver’. The device which controls the signal is
called the ‘master’. The devices that are controlled by the
master are called ‘slaves’.
Each byte is followed by one acknowledge bit. This
acknowledge bit is a HIGH level, put on the bus by the
transmitter. The master generates an extra acknowledge
related clock pulse. The slave receiver which is addressed
is obliged to generate an acknowledge after the reception
of each byte.
The master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse in such a way that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse.
Set-up and hold times must be taken into account.
A master receiver must signal an end of data to the slave
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master generation of the STOP condition.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PCF8523 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Real-Time Clock (RTC) and calendar |
| PCF8523T | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Save power with small, ultra-efficient RTCs |
| PCF8523T/1,118 | 功能描述:实时时钟 REAL-TIME CLOCK (RTC) AND CALENDAR RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| PCF8523T/1,118-CUT TAPE | 制造商:NXP 功能描述:PCF8523 Series 5.5 V 1 Mbps I2C Interface Real Time Clock / Calendar - SOIC-8 |
| PCF8523T-1 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Real-Time Clock (RTC) and calendar |
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