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参数资料
| 型号： | PCF8566T/1,118 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 15/48页 |
| 文件大小： | 0K |
| 描述： | IC LCD DVR UNVRSL LOW-MUX 40VSOP |
| 产品培训模块： | LCD Driver I²C Bus Fundamentals |
| 特色产品： | NXP - I2C Interface |
| 标准包装： | 1 |
| 显示器类型： | LCD |
| 配置： | 7 段 + DP，14 段（24 段） |
| 接口： | I²C |
| 电流 - 电源： | 30µA |
| 电源电压： | 2.5 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-BSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 40-VSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 844 (CN2011-ZH PDF) |
| 其它名称： | 568-1070-6 |
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NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF8566 are timed by the frequency
f clk , which equals either the built-in oscillator frequency f osc or the external clock frequency
f clk(ext) .
The clock frequency (f clk ) determines the LCD frame frequency (f fr ) and the maximum rate
for data reception from the I 2 C-bus. To allow I 2 C-bus transmissions at their maximum data
rate of 100 kHz, f clk should be chosen to be above 125 kHz.
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to pin V SS . In this case, the
output from pin CLK is the clock signal for any cascaded PCF8566s or PCF8576s in the
system.
7.5.2 External clock
Connecting pin OSC to V DD enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device. Removing the clock,
freezes the LCD in a DC state.
7.6 Timing
The timing of the PCF8566 sequences the internal data ?ow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between the PCF8566s in the system. The timing also generates the LCD
frame frequency which is derived as an integer division of the clock frequency (see
used or by the frequency applied to the pin CLK when an external clock is used.
Table 6.
LCD frame frequencies [1]
f fr = -------------
f fr = ----------
PCF8566 mode
normal mode
power saving mode
Frame frequency
f clk
2880
f clk
480
Nominal frame frequency (Hz)
69 [2]
65 [3]
[1]
[2]
[3]
For f clk = 200 kHz.
For f clk = 31 kHz.
The ratio between the clock frequency and the LCD frame frequency depends on the
mode in which the device is operating. In the power-saving mode the reduction ratio is six
times smaller; this allows the clock frequency to be reduced by a factor of six. The
reduced clock frequency results in a signi?cant reduction in power dissipation.
PCF8566_7
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
15 of 48
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PCF8566TD | 功能描述:LCD 驱动器 96 SGMT LCD SGMT DRV RoHS:否 制造商:Maxim Integrated 数位数量:4.5 片段数量:30 最大时钟频率:19 KHz 工作电源电压:3 V to 3.6 V 最大工作温度:+ 85 C 最小工作温度:- 20 C 封装 / 箱体:PDIP-40 封装:Tube |
| PCF8566TD-T | 制造商:NXP Semiconductors 功能描述:LCD DRVR 12DIGIT 3.3V/5V 40-Pin VSO T/R |
| PCF8566TS | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCF8566TS/1,112 | 功能描述:LCD 驱动器 24 SGMT 315KHz RoHS:否 制造商:Maxim Integrated 数位数量:4.5 片段数量:30 最大时钟频率:19 KHz 工作电源电压:3 V to 3.6 V 最大工作温度:+ 85 C 最小工作温度:- 20 C 封装 / 箱体:PDIP-40 封装:Tube |
| PCF8566TS/1,118 | 功能描述:LCD 驱动器 24 SGMT 315KHz RoHS:否 制造商:Maxim Integrated 数位数量:4.5 片段数量:30 最大时钟频率:19 KHz 工作电源电压:3 V to 3.6 V 最大工作温度:+ 85 C 最小工作温度:- 20 C 封装 / 箱体:PDIP-40 封装:Tube |
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