参数资料
型号: PCF8579H/1:118
厂商: NXP Semiconductors
文件页数: 15/41页
文件大小: 0K
描述: IC LCD COLUMN DRIVER 64-LQFP
标准包装: 1,500
显示器类型: LCD
配置: 点阵
接口: I²C
电流 - 电源: 9µA
电源电压: 2.5 V ~ 6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
其它名称: 935276303118
PCF8579H/1-T
PCF8579H/1-T-ND
NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
8.6.5 I 2 C-bus controller
The I 2 C-bus controller detects the I 2 C-bus protocol, slave address, commands and display
data bytes. It performs the conversion of the data input (serial-to-parallel) and the data
output (parallel-to-serial). The PCF8579 acts as an I 2 C-bus slave transmitter/receiver.
Device selection depends on the I 2 C-bus slave address, the hardware subaddress and
the commands transmitted.
8.6.6 Input ?lters
To enhance noise immunity in electrically adverse environments, RC low-pass ?lters are
provided on the SDA and SCL lines.
8.6.7 I 2 C-bus protocol
Two 7-bit slave addresses (0111100 and 0111101) are reserved for both the PCF8578
and PCF8579. The least signi?cant bit of the slave address is set by connecting input SA0
to either logic 0 (V SS ) or logic 1 (V DD ). Therefore, two types of PCF8578 or PCF8579 can
be distinguished on the same I 2 C-bus which allows:
1. One PCF8578 to operate with up to 32 PCF8579s on the same I 2 C-bus for very large
applications (see Table 16 ).
2. The use of two types of LCD multiplex schemes on the same I 2 C-bus.
In most applications the PCF8578 will have the same slave address as the PCF8579.
The I 2 C-bus protocol is shown in Figure 13 . All communications are initiated with a START
condition (S) from the I 2 C-bus master, which is followed by the desired slave address and
read/write bit. All devices with this slave address acknowledge in parallel. All other devices
ignore the bus transfer.
In WRITE mode (indicated by setting the read/write bit LOW) one or more commands
follow the slave address acknowledgement. The commands are also acknowledged by all
addressed devices on the bus. The last command must clear the continuation bit C.
After the last command a series of data bytes may follow. The acknowledgement after
each byte is made only by the (A0, A1, A2 and A3) addressed PCF8579 or PCF8578 with
its implicit subaddress 0. After the last data byte has been acknowledged, the I 2 C-bus
master issues a STOP condition (P).
In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read from
the RAM following the slave address acknowledgement. After this acknowledgement the
master transmitter becomes a master receiver and the PCF8579 becomes a slave
transmitter. The master receiver must acknowledge the reception of each byte in turn. The
master receiver must signal an end of data to the slave transmitter, by not generating an
acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves
the data line HIGH, enabling the master to generate a STOP condition (P).
Display bytes are written into, or read from the RAM at the address speci?ed by the data
pointer and subaddress counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be transferred either to, or from
the intended devices.
PCF8579_5
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 May 2009
15 of 41
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