参数资料
| 型号： | PCM1602APTG4 |
| 厂商： | Texas Instruments |
| 文件页数： | 7/46页 |
| 文件大小： | 0K |
| 描述： | IC DAC 24BIT 6CH 192KHZ 48-LQFP |
| 产品培训模块： | Data Converter Basics |
| 标准包装： | 250 |
| 位数： | 24 |
| 数据接口： | 串行 |
| 转换器数目： | 6 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 240mW |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 6 电压，单极 |
| 采样率（每秒）： | 192k |
| 配用： | DEM-DAI1602-ND - EVAL FIXTURE FOR PCM1602 |
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www.ti.com
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1602A consists of a 5-wire synchronous serial port. It includes LRCK (pin
41), BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), and DATA3 (pin 47). BCK is the serial audio bit clock, and is
used to clock the serial data present on DATA1, DATA2, and DATA3 into the audio interface serial shift register.
Serial data is clocked into the PCM1602A on the rising edge of BCK. LRCK is the serial audio left/right clock. It is
used to latch serial data into the serial audio interface internal registers.
Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK
be derived from the system clock input, SCKI. LRCK is operated at the sampling frequency (fS). BCK can be
operated at 32, 48, or 64 times the sampling frequency (I2S format does not support BCK = 32 fS).
Internal operation of the PCM1602A is synchronized with LRCK. Accordingly, internal operation of the device is
suspended when the sampling rate clock (LRCK) is changed, or when SCKI and/or BCK is interrupted at least for
a 3-bit clock cycle. If SCKI, BCK, and LRCK are provided continuously after this suspended state, the internal
operation is resynchronized automatically within a period of less than 3/fS. During this resynchronization period
and for a 3/fS time thereafter, the analog outputs are forced to the bipolar zero level, VCC/2. External resetting is
not required.
AUDIO DATA FORMATS AND TIMING
The PCM1602A supports industry-standard audio data formats, including standard, I2S, and left-justified (see
Figure 22). Data formats are selected using the format bits, FMT[2:0], in register 9. The default data format is
24-bit standard. All formats require binary 2s complement, MSB-first audio data. See Figure 23 for a detailed
timing diagram of the serial audio interface.
DATA1, DATA2, and DATA3 each carry two audio channels, designated as the left and right channels. The
left-channel data always precedes the right-channel data in the serial data stream for all data formats. Table 2
shows the mapping of the digital input data to the analog output pins.
Copyright 2005–2010, Texas Instruments Incorporated
15
Product Folder Link(s): PCM1602A
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