参数资料
型号: PCM1792DBRG4
厂商: Texas Instruments
文件页数: 18/61页
文件大小: 0K
描述: IC DAC 24BIT STER 192KHZ 28-SSOP
产品培训模块: Data Converter Basics
标准包装: 2,000
位数: 24
数据接口: I²C,串行,SPI?
转换器数目: 2
电压电源: 模拟和数字
工作温度: -25°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 带卷 (TR)
输出数目和类型: 2 电压,单极
采样率(每秒): 200k
PCM1792
SLES069B MARCH 2003 REVISED NOVEMBER 2006
www.ti.com
25
TIMING DIAGRAM
SDA
SCL
t(BUF)
t(D-SU)
t(D-HD)
Start
t(LOW)
t(S-HD)
t(SCL-F)
t(SCL-R)
t(HI)
Repeated Start
t(RS-SU)
t(RS-HD)
t(SDA-F)
t(SDA-R)
t(P-SU)
Stop
t(SP)
TIMING CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
MAX
UNIT
f(SCL)
SCL clock frequency
Standard
100
kHz
f(SCL)
SCL clock frequency
Fast
400
kHz
t(BUF)
Bus free time between stop and start conditions
Standard
4.7
s
t(BUF)
Bus free time between stop and start conditions
Fast
1.3
s
t(LOW)
Low period of the SCL clock
Standard
4.7
s
t(LOW)
Low period of the SCL clock
Fast
1.3
s
t(HI)
High period of the SCL clock
Standard
4
s
t(HI)
High period of the SCL clock
Fast
600
ns
t(RS-SU)
Setup time for (repeated) start condition
Standard
4.7
s
t(RS-SU)
Setup time for (repeated) start condition
Fast
600
ns
t(S-HD)
Hold time for (repeated) start condition
Standard
4
s
t(RS-HD)
Hold time for (repeated) start condition
Fast
600
ns
t(D-SU)
Data setup time
Standard
250
ns
t(D-SU)
Data setup time
Fast
100
ns
t(D-HD)
Data hold time
Standard
0
900
ns
t(D-HD)
Data hold time
Fast
0
900
ns
t(SCL-R)
Rise time of SCL signal
Standard
20 + 0.1 CB
1000
ns
t(SCL-R)
Rise time of SCL signal
Fast
20 + 0.1 CB
300
ns
t(SCL-R1)
Rise time of SCL signal after a repeated start condition and after an
Standard
20 + 0.1 CB
1000
ns
t(SCL-R1)
Rise time of SCL signal after a repeated start condition and after an
acknowledge bit
Fast
20 + 0.1 CB
300
ns
t(SCL-F)
Fall time of SCL signal
Standard
20 + 0.1 CB
1000
ns
t(SCL-F)
Fall time of SCL signal
Fast
20 + 0.1 CB
300
ns
t(SDA-R)
Rise time of SDA signal
Standard
20 + 0.1 CB
1000
ns
t(SDA-R)
Rise time of SDA signal
Fast
20 + 0.1 CB
300
ns
t(SDA-F)
Fall time of SDA signal
Standard
20 + 0.1 CB
1000
ns
t(SDA-F)
Fall time of SDA signal
Fast
20 + 0.1 CB
300
ns
t(P-SU)
Setup time for stop condition
Standard
4
s
t(P-SU)
Setup time for stop condition
Fast
600
ns
C(B)
Capacitive load for SDA and SCL line
400
pF
t(SP)
Pulse duration of suppressed spike
Fast
50
ns
VNH
Noise margin at high level for each connected device (including hysteresis)
Standard
VNH
Noise margin at high level for each connected device (including hysteresis)
Fast
0.2 VDD
V
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