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参数资料
| 型号： | PCM3794RHBRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQCC32 |
| 封装： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 11/67页 |
| 文件大小： | 1417K |
| 代理商： | PCM3794RHBRG4 |
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t
w(SCKH)
SCKI
t
w(SCKL)
0.7V
IO
0.3V
IO
T0005-12
Power-On Reset and System Reset
Power On/Off Sequence
SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007
PARAMETERS
SYMBOL
MIN
UNITS
System-clock pulse duration, high
tw(SCKH)
7
ns
System-clock pulse duration, low
tw(SCKL)
7
ns
Figure 25. System Clock Timing
The power-on-reset circuit outputs a reset signal, typically at VDD = 1.2 V, and this circuit does not depend on
the voltage of other power supplies (VCC, VPA and VIO). Internal circuits are cleared to default status, then signals
are removed from all analog and digital outputs. The PCM3793/94 does not require any power supply
sequencing. Register data must be written after turning all power supplies on.
System reset is enabled by setting register 85 (SRST), and all register are cleared automatically. All circuits are
reset to their default status at once. Note that the PCM3793/94 has audible pop noise on the analog outputs
when enabling SRST.
To reduce audible pop noise, a sequence of register settings is required after turning all power supplies on when
powering up, or before turning the power supplies off when powering down. If some modules are not required for
a particular application or operation, they should be placed in the power-down state after performing the
power-on sequence. The recommended power-on and power-off sequences are shown in Table 3 and Table 4,
respectively.
Table 3. Recommended Power-On Sequence
STEP
REGISTER
NOTE
SETTINGS
1
–
Turn on all power supplies(1)
2
4027h
Headphone amplifier L-ch volume (–6 dB)(2)
3
4127h
Headphone amplifier R-ch volume (–6 dB)(2)
4
4227h
Speaker amplifier L-ch volume (–6 dB)(2)
5
4327h
Speaker amplifier R-ch volume (–6 dB)(2)
6
4427h
Digital attenuator L-ch (–24 dB)(2)
7
4527h
Digital attenuator R-ch (–24 dB)(2)
8
4620h
DAC audio interface format (left-justified)(3)
9
4BC0h
Headphone detection enable and inverting polarity. Short and thermal detection enable
10
5102h
ADC audio interface format (left-justified)(3)
11
5A10h
VCOM ramp up/down time control. PG1, PG2 gain control (0 dB)
12
49E0h
DAC (DAL, DAR) and analog bias power up
13
5601h
Zero-cross detection enable
14
4803h
Analog mixer (MXL, MXR) power up
15
5811h
Analog mixer input (SW2, SW5) select
16
49FCh
Headphone amplifier (HPL, HPR, HPC) power up
(1)
Power supply sequencing is not required. It is recommended to set register data with system clock input after turning all power supplies
on.
(2)
Any level is acceptable for volume or attenuation. Level should be resumed by register data recorded when system power off.
(3)
Audio interface format should be set to match the DSP or decoder being used.
19
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