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参数资料
| 型号： | PD70101ILQ |
| 厂商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封装： | 5 X 5 MM, ROHS COMPLIANT, PLASTIC, QFN-32 |
| 文件页数： | 9/19页 |
| 文件大小： | 416K |
| 代理商： | PD70101ILQ |
PD70101 & PD70201
PRELIMINARY DATA SHEET
Copyright 2010
Microsemi
Page 17
Rev. 0.6, 21-Jan-2011
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA 92841; 714-898-8121; Fax: 714-893-2570
P
D
7
0
1
0
1
&
P
D
7
0
2
0
1
PD70101 / PD70201: IEEE 802.3 af/at
Power Over Ethernet PD Controller
TM
T H E O R Y O F O P E R A T I O N
This discharge continues until VSS = 50 mV where an
internal ~50 MOSFET connected to SS turns on for 25
clock cycles to ensure the SS capacitor fully discharges to
GND before ramping back up and restart. The converter
will exit the hiccup mode when the over current condition is
removed or the four consecutive event counter has been
reset.
If the over current condition lasts less than four
consecutive cycles, the four event counter is reset to start
the recount again.
LOW POWER MODE OPERATION
The devices offer a pulse skipping operation for light load
condition, referred as Low Power Mode (LPM), to improve
the efficiency of light load operation by reducing the power
dissipation especially in high frequency switching. Using
an external resistor from RCLP pin to GND, the user can
program the output power when the unit enters pulse
skipping.
Pulse skipping mode is disabled until SS ramp is
completed, regardless of the LPM status.
INPUT (VPP &VCC) UNDER VOLTAGE LOCK OUT
The PD interface circuit offers a PGOOD signal that can
be used to start the DC-DC converter; however the
threshold of the PGOOD is fixed at VPNO-VPNI ≤ 0.7V.
This may not fit all possible applications.
Therefore the
devices offers an option to have a programmable UVLO
which is tied to level of VPP-VPNO, plus a programmable
hysteresis.
The voltage developed across a simple
resistor divider is sensed at VINS, and will enable/disable
the PWM controller at a nominal 1.2V threshold. A third
resistor connected between VINS and HYST pins allows
programmable hysteresis.
This feature enables the end
user to tailor to any desired systems application’s
requirement for turn on and turn off time. In addition to the
VPP sensing for UVLO, the devices also have VCC UVLO
to ensure that the PWM controller is always properly
powered during operation. These features provide robust
solutions under various systems disturbances.
POWER FAIL WARNING
A Power Fail Warning feature is also offered as an option
in lieu of VPP UVLO, to fit applications that require PFW
more than VPP UVLO. The PFW uses the same resistor-
divider connected to VINS to sense the input voltage
(VPP). The nominal 1.2V threshold level is set by the user
at a point above the VPP voltage level where DC-DC
output voltage drop out occurs due to maximum duty cycle
limit.
This warning lets the system know in advance
before the output starts to drop.
As with the VPP UVLO function, hysteresis is
controlled by a resistor connected between the HYST
and VINS pins.
The warning time depends on the output power,
conversion efficiency, the input capacitor and the
detection threshold setting relative to the input drop
out voltage meaning the difference between the VPP
setting threshold and the drop out voltage (VPP_
THRESHOLD – VDROPOUT).
Warning time can be calculated by:
TWARN =
ηC (V1
2 – V
2
2)/2Po
Where:
C = DC-DC Input Bulk Capacitance
V1 = VPP_THRESHOLD
V2 = VDROPOUT
Po is the instantaneous output power.
For example: if C = 200 F, V1 = 42 V, V2 = 36 V and
Po = 25 W,
η = 0.87(efficiency), then
TWARN = 1.63 ms.
VIN_SEL
The Power Fail Warning and VPP UVLO functions are
user selectable via the VINS_SEL pin. Pin function is
defined in Table 1:
VINS_SEL
VINS
> 1.2V
Operation
Comment
GND
Don’t
care
PFW
DC-DC
controller is
enabled
depending on
VCC and EN
pins
VL
No
VPPUVLO
DC-DC
controller is not
enabled.
VL
Yes
VPPUVLO
DC-DC
controller is
enabled
depending on
VCC and EN
pins
Table 1 – VINS_SEL Pin Function
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