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参数资料
| 型号： | PDM31034SA10TSO |
| 元件分类： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 10 ns, PDSO32 |
| 文件页数： | 7/8页 |
| 文件大小： | 309K |
| 代理商： | PDM31034SA10TSO |
PRELIMINARY
PDM31034
Rev. 1.4 - 4/17/98
7
1
2
3
4
5
6
7
8
9
10
11
12
Write Cycle No. 3 (Chip Enable Controlled)
AC Electrical Characteristics
NOTES: (For two previous Electrical Characteristics tables)
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.
2. At any given temperature and voltage condition, tHZCE is less than tLZCE.
3. This parameter is sampled.
4. WE is high for a READ cycle.
5. The device is continuously selected. Chip Enable is held in their active state.
6. The address is valid prior to or coincident with the latest occuring Chip Enable.
Description
-9
-10
-12
-15
-20
WRITE Cycle
Sym
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
WRITE cycle time
tWC
9
10121520
ns
Chip enable active time
tCW
8
9
10
11
12
ns
Address valid to end of write
tAW
8
9
10
11
12
ns
Address setup time
tAS
00000
ns
Address hold from end of write
tAH
00000
ns
Write pulse width
tWP
7
8
9
10
11
ns
Data setup time
tDS
56789
ns
Data hold time
tDH
00000
ns
Write disable to output in low Z(1,3)
tLZWE
00000
ns
Write enable to output in high Z(1,3)
tHZWE
67789
ns
NOTE: Output Enable (OE) is inactive (high)
tWC
tAW
tWP
tCW
tAH
tAS
tDH
tDS
ADDR
CE
WE
DOUT
HIGH-Z
DIN
DATA VALID
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PDM31096 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4 Megabit 3.3V Static RAM 512K x 8-Bit |
| PDM31096SA10SO | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4 Megabit 3.3V Static RAM 512K x 8-Bit |
| PDM31096SA10SOA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4 Megabit 3.3V Static RAM 512K x 8-Bit |
| PDM31096SA10SOATR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4 Megabit 3.3V Static RAM 512K x 8-Bit |
| PDM31096SA10SOATY | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4 Megabit 3.3V Static RAM 512K x 8-Bit |
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