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参数资料
| 型号： | PE33631MLIAA-Z |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE DETECTOR, QCC64 |
| 封装： | 9 X 9 MM, GREEN, QFN-64 |
| 文件页数： | 11/16页 |
| 文件大小： | 295K |
| 代理商： | PE33631MLIAA-Z |
Advance Information
PE33631
Page 4 of 16
2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0291-01
│ UltraCMOS RFIC Solutions
Pin No.
Pin
Name
Valid
Mode
Type
Description
49
GND
Downbond
Ground
50
fr
Both
Input
Reference frequency input.
51
VDD
(Note 1)
Reference VDD.
52
VDD
(Note 1)
Digital core VDD.
53
ENHB
Both
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
54
MS2_SEL
Both
Input
MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
55
RAND_SEL
Both
Input
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 219.
56
R0
Direct
Input
R Counter bit0 (LSB).
57
R1
Direct
Input
R Counter bit1.
58
R2
Direct
Input
R Counter bit2.
59
R3
Direct
Input
R Counter bit3.
60
R4
Direct
Input
R Counter bit4.
61
R5
Direct
Input
R Counter bit5 (MSB).
62
K0
Direct
Input
K Counter bit0 (LSB).
63
K1
Direct
Input
K Counter bit1.
64
VDD
(Note 1)
Digital core VDD.
Note 1:
All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
Note 2:
All digital input pins have 70 k
pull-down resistors to ground.
Table 1. Pin Descriptions (continued)
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