参数资料
型号: PE42510AMLI-Z
厂商: Peregrine Semiconductor
文件页数: 1/7页
文件大小: 0K
描述: IC RF SWITCH SPDT 50 OHM 32-QFN
标准包装: 1
系列: UltraCMOS™
RF 型: 通用
频率: 30MHz ~ 2GHz
特点: SPDT
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 标准包装
其它名称: 1046-1049-6
Product Specification
PE42510A
The PE42510A is manufactured on Peregrine’s UltraCMOS
Product Description
The following specification defines an SPDT (single pole
double throw) switch for use in cellular and other wireless
applications. The PE42510A uses Peregrine’s UltraCMOS ?
process and it also features HaRP? technology
enhancements to deliver high linearity and exceptional
harmonics performance. HaRP? technology is an innovative
feature of the UltraCMOS ? process providing upgraded
linearity performance.
?
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Diagram
SPDT High Power UltraCMOS ?
Reflective RF Switch 30 - 2000 MHz
Features
?? No blocking capacitors required
?? 50 Watt P1dB compression point
?? 10 Watts <8:1 VSWR (Normal Operation)
?? 29 dB Isolation @ 800 MHz
?? <0.3 dB Insertion Loss at 800 MHz
?? 2f o and 3f o < -84 dBc @ 42.5 dBm
?? ESD rugged to 2.0 kV HBM
?? 32-lead 5x5x0.85 mm QFN package
Figure 2. Package Type
32-lead 5x5x0.85 mm
71-0014
Table 1. Electrical Specifications @ 25°C, V DD = 3.3V (Z S = Z L = 50 ? ) unless otherwise noted
Parameter
RF Insertion Loss
0.1 dB Input Compression Point
Isolation (Supply Biased): RF to RFC
Unbiased Isolation: RF - RFC, V DD , V1=0V
RF (Active Port) Return Loss
2nd Harmonic
3rd Harmonic
Switching Time 2,3
Conditions
30 MHz ≤ 1 GHz
1 GHz < 2 GHz
800 MHz, 50% duty cycle
800 MHz
27 dBm, 800 MHz
800 MHz @ +42.5 dBm
50% of CTRL to 10/90% of RF
Min
25
5
15
Typ
0.4
0.5
45.4
29
22
-84
25
Max
0.6
0.7
-81
31
Units
dB
dB
dBm
dB
dB
dB
dBc
μs
Notes: 1. The device was matched with 1.6 nH inductance per RF port
2. For high power applications, harmonics settling needs to be accounted for. Harmonics settling time is defined to be 50% of CTRL to
2fo/3fo within 3 dB of final value
3. For RF input power (50 ? ) > 31 dBm, and operation above 30 MHz, the switching time and harmonics settling time is 100 μs Max
Document No. 70-0266-03 │ www.psemi.com
?2008-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 7
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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