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| 型号： | PE42556DI-Z |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 5/9页 |
| 文件大小： | 0K |
| 描述： | IC RF SWITCH SPDT FLIP CHIP |
| 标准包装： | 1,000 |
| 系列： | UltraCMOS™, HaRP™ |
| RF 型： | 手机 |
| 频率： | 9kHz ~ 13.5GHz |
| 特点： | SPDT |
| 封装/外壳： | 14-XFBGA，FCDSBGA |
| 供应商设备封装： | 14-覆晶式 |
| 包装： | 带卷 (TR) |
| 其它名称： | PE42556 |
PE42556
Product Brief
Evaluation Kit
The SPDT switch EK Board was designed to ease
customer evaluation of Peregrine's PE42556 (dual
use with PE42554). The RF Common port is
connected through a 50 ohm transmission line via
the top SMA connector, J1. RF1 and RF2 are
connected through 50 ohm transmission lines via
SMA connectors J3, and J2, respectively. A
through 50 ohm transmission line is available via
SMA connectors J4 and J5. This transmission line
can be used to estimate the loss of the PCB over
the environmental conditions being evaluated.
The board is constructed of a four metal layers
with a total thickness of 62 mils. The top and
bottom layers are ROGERS RO4003 material with
an 8 mil core and Er = 3.55. The middle layers
Figure 6. Evaluation Board Layouts
Peregrine Specification 101/0402
X
provide ground for the transmission lines. The RF
transmission lines were designed using a coplanar
waveguide with ground plane model using a trace
width of 15 mils, and trace gaps of 10 mils.
Figure 7. Evaluation Board Schematic
Peregrine Specification 102/0478
J9
HEADER, 12 PIN
General Comments
--
Transmission lines connected to J1, J2, and J3 should
have exactly the same electrical length.
The path from J2 to J3 including the distance through the part
should have the same length as J4 and J5 and be in parallel to
J4 to J5.
1
3
5
7
9
11
CTL
LS
NC
VDD
VSS
GND
GND
GND
GND
GND
GND
GND
2
4
6
8
10
12
NOTES:
1. USE 101-0402-02 PCB
U1
PE42554
2
J3
RF1
8
1
J1
1
2
6
RFC
RF2
4
2
J2
1
J4
2
2
J5
1
Document No. DOC-50245-2 │ www.psemi.com
Visit psemi.com for full version of datasheet
1
?2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 9
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