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| 型号： | PE4256MLIAA-Z |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 4/8页 |
| 文件大小： | 0K |
| 描述： | IC RF SWITCH SPDT 75 OHM 20-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| RF 型： | CATV |
| 频率： | 5MHz ~ 3GHz |
| 特点： | SPDT |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（4x4） |
| 包装： | 标准包装 |
| 其它名称： | 1046-1040-6 |
PE4256
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit was designed to
Figure 4. Evaluation Board Layouts
Peregrine Specification 101/0148~03A
ease customer evaluation of the PE4256 SPDT
switch. The RF common port (RFC) is connected
through a 75 ? transmission line to J2. Port 1 and
Port 2 are connected through 75 ? transmission
lines to J1 and J3. A through transmission line
connects F connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed with four metal layers in
FR4 material with a total thickness of 0.062". The
transmission lines were designed using a coplanar
waveguide with ground plane (28 mil core, 21 mil
width, 30 mil gap).
J6 provides a means for controlling DC and digital
inputs to the device. The provided jumpers short
the package pin to ground for logic low. When the
jumper is removed, the pin is pulled up to V DD for
logic high.
When the jumper is in place, 3 μA of current will
flow through the 1 M ? pull-up resistor. This extra
current should not be attributed to the device.
Proper PCB design is essential for full isolation
performance. This evaluation board demonstrates
good trace and ground management for minimum
coupling and radiation.
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0195~02A
?2010-2011 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0144-04 │ UltraCMOS? RFIC Solutions
Page 4 of 8
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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