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参数资料
| 型号： | PE43503MLI-Z |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 5/11页 |
| 文件大小： | 983K |
| 描述： | IC RF DSA 5BIT 50 OHM 24QFN |
| 标准包装： | 3,000 |
| 系列： | UltraCMOS™, HaRP™ |
| 衰减值： | 0dB ~ 31dB |
| 容差： | ±0.3dB |
| 频率范围： | 9kHz ~ 6GHz |
| 阻抗： | 50 欧姆 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 其它名称： | PE43503 |
Product Specification
PE43503
Page 5 of 11
Document No. 70-0252-05 www.psemi.com
?008-2009 Peregrine Semiconductor Corp. All rights reserved.
Table 5. Control Voltage
Table 6. Latch and Clock Specifications
Table 8. Attenuation Word Truth Table
Parallel Control Setting
Attenuation Setting
RF1-RF2
D6
D5
D4
D3
D2
L
L
L
L
L
Reference I.L.
L
L
L
L
H
1 dB
L
L
L
H
L
2 dB
L
L
H
L
L
4 dB
L
H
L
L
L
8 dB
H
L
L
L
L
16 dB
H
H
H
H
H
31 dB
Table 7. Parallel Truth Table
State
Bias Condition
Low
0 to +1.0 Vdc at 2 礎 (typ)
High
+2.6 to +5 Vdc at 10 礎 (typ)
Latch Enable
Function
X
Shift Register Clocked
?
Contents of shift register
transferred to attenuator core
Shift Clock
?
X
Attenuation Word
Attenuation
Setting
RF1-RF2
D7 D6 D5 D4 D3 D2 D1
D0
(LSB)
L
L
L
L
L
L
L
L
Reference I.L.
L
L
L
L
L
H
L
L
1 dB
L
L
L
L
H
L
L
L
2 dB
L
L
L
H
L
L
L
L
4 dB
L
L
H
L
L
L
L
L
8 dB
L
H
L
L
L
L
L
L
16 dB
L
H
H
H
H
H
L
L
31 dB
Table 9. Serial Register Map
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D7
D6
D5
D4
D3
D2
D1
D0
Attenuation Word
LSB (first in)
MSB (last in)
Bits must be set to logic low
Attenuation Word is derived directly from the attenuation value. For example, to program the 13 dB state:
Attenuation Word: Multiply by 4 and convert to binary ?4 *13 dB ?52 ?00110100
Serial Input: 00110100
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