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| 型号： | PEF20570 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | DSP Embedded Line and Port Interface Controller |
| 中文描述： | DSP嵌入式线和港口接口控制器 |
| 文件页数： | 2/8页 |
| 文件大小： | 170K |
| 代理商： | PEF20570 |
PEB 20570/PEF 20570
PEB 20571/PEF 20571
Addendum to “DELIC Clock System Synchronization”
Addendum
2/8
2003-08-04
1.1
Clocking the VIP in LT-T Mode by DELIC Layer 1 Clock
Figure 1
Clocking the VIP by using DELIC Layer 1 Clock
When the Central Office is activated, its clock signal is retrieved by the RxPLL of the VIP
and a 1.536 MHz reference signal is generated and used as input signal for the DELIC
DCXO (pin XCLK). This signal is divided down to 8 kHz and used as input for the DCXO
phase detector (PD). The second input to PD is another 8 kHz signal which originates
from the 16.384 MHz output of the DCXO.
The DELIC PLL multiplies the 16.384 MHz DCXO signal up to 61.44 MHz. A divider
generates the 15.36 MHz layer 1 clock which is used to clock the VIP.
When the Central Office is deactivated, the VIP takes its oscillator signal of 15.36 MHz
(the DELIC Layer 1 clock) divided by 10 and uses this signal as DELIC XCLK input as
replacement of the Central Office clock.
As a consequence, the DELIC DCXO gets its own signal as input for the PD. Since the
second PD input is also generated by the DCXO, the PLL system is unstable. This
results in the DCXO and the PLL running to its respective corner frequency. Therefore,
the 100 ppm clock accuracy, required by ITU-T I.430, cannot be guaranteed during this
time. When switching to another clock source (REFCLK), the DELIC DCXO will work
properly again.
DELIC_refclk1
VIP
Central
Office
OSC
RxPLL
DCXO
/10
Mux
15.36 MHz
16.384 MHz
Divider
PD
PLL
Divider
1.536 MHz
Divider
8kHz
XCLK
REFCLK
16.384 MHz
DELIC
L1_CLK
INCLK
MUX
REFCLK
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相关代理商/技术参数 |
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| PEF20570FV3.1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| PEF20571FV31XP | 制造商:Lantiq 功能描述:XWAY DELIC -LC/PB - PEF 20570/71 WIRELINE COMMUNICATION PRODUCTS |
| PEF20580FV3.1 | 制造商:Infineon Technologies AG 功能描述: |
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