参数资料
型号: PEF20571
厂商: INFINEON TECHNOLOGIES AG
英文描述: DSP Embedded Line and Port Interface Controller
中文描述: DSP嵌入式线和港口接口控制器
文件页数: 7/8页
文件大小: 170K
代理商: PEF20571
PEB 20570/PEF 20570
PEB 20571/PEF 20571
DELIC Strap Option Configuration
Addendum
7/8
2003-08-04
4
DELIC Strap Option Configuration
The DELIC “
Strap Status Register (CSTRAP)
” is described in the DELIC-LC PEB
20570/DELIC-PB PEB 20571 Data Sheet, independent of the version (2.1 .. 3.1). The
register description (see updated register
CSTRAP
) of the Data Sheet is misleading
concerning bit 0 and 1. They are
not
configured by strap option. For a stable DCXO
synchronization it is recommended to proceed as follows:
1. After Boot read register CSTRAP to detect the value
2. Set only bit CSTRAP:
DCXO
to ’
0
’ and set the others as detected before
CSTRAP
Strap Status Register
(D08F
H
) Reset Value: 0000 0xxx xxxx xx10
B
15
14
13
12
11
10
9
8
Res
STRAP
rw
rw
7
6
5
4
3
2
1
0
STRAP
DCXO
ISCD
rw
rw
rw
Field
Res
Bits
[15:11] rw
Type Description
Reserved
Returns 0 upon read; must be written with 0.
rw
STRAP Pin Definition
This register enables the OAK
to read the strap values
sampled during reset.
Bit
Function
10
PCM Clock Master Strap
9:7
Test Mode Strap
6
Emulation Boot Strap
5
PLL Bypass Strap
4
DSP PLL Power-Down Strap
3
Boot Strap
2
Reset counter Bypass Strap
rw
DCXO Synchronization Config
0
Linear (slow) synchronization
1
Fast synchronization (default)
STRAP
[10:2]
DCXO
1
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