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参数资料
| 型号： | PEX8632 |
| 厂商： | PLX Technology, Inc. |
| 英文描述： | PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch |
| 中文描述： | 的PCIe Gen2，5.0GT / s的32通道，12端口交换机 |
| 文件页数： | 1/4页 |
| 文件大小： | 209K |
| 代理商： | PEX8632 |
Preliminary - PLX Confidential
PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch
Features
PEX 8632 General Features
o
32-lane, 12-port PCIe Gen2 switch
-
Integrated 5.0 GT/s SerDes
o
27 x 27mm
2
, 676-pin FCBGA package
o
Typical Power: < 5.5 Watts
PEX 8632 Key Features
o
Standards Compliant
-
PCI Express Base Specification, r2.0
(backwards compatible w/ PCIe r1.0a/1.1)
-
PCI Power Management Spec, r1.2
-
Microsoft Vista Compliant
-
Supports Access Control Services
-
Dynamic link-width control
-
Dynamic SerDes speed control
o
High Performance
-
Non-blocking switch fabric
-
Full line rate on all ports
-
Packet Cut-Thru with 145ns max packet
latency (x8 to x8)
-
2KB Max Payload Size
-
Read Pacing (bandwidth throttling)
-
Dual-Cast
o
Flexible Configuration
-
Ports configurable as x1, x2, x4, x8, x16
-
Registers configurable with strapping
pins, EEPROM, I
2
C, or host software
-
Lane and polarity reversal
-
Compatible with PCIe 1.0a PM
o
Dual-Host & Fail-Over Support
-
Configurable Non-Transparent port
-
Moveable upstream port
-
Crosslink port capability
o
Quality of Service (QoS)
-
Eight traffic classes per port
-
Weighted round-robin source
port arbitration
o
Reliability, Availability, Serviceability
-
3 Hot Plug Ports with native HP Signals
-
All ports hot plug capable thru I
C
(Hot Plug Controller on every port)
-
ECRC and Poison bit support
-
Data Path parity
-
Memory (RAM) Error Correction
-
INTA# and FATAL_ERR# signals
-
Advanced Error Reporting
-
Port Status bits and GPIO available
-
Per port error diagnostics
-
Performance Monitoring
Per port payload & header counters
-
JTAG AC/DC boundary scan
The
ExpressLane
TM
PEX 8632 device offers PCI Express switching
capability enabling users to add scalable high bandwidth, non-blocking
interconnection to a wide variety of applications including
servers,
storage systems, and communications platforms.
The PEX 8632 is
well suited for
fan-out
,
aggregation, and peer-to-peer
applications.
High Performance & Low Packet Latency
The PEX 8632 architecture supports packet
cut-thru with a maximum
latency of 145ns (x8 to x8).
This, combined with large packet memory and
non-blocking internal switch architecture, provides full line rate on all ports
for performance-hungry applications such as
servers
and
switch fabrics
.
The low latency enables applications to achieve high throughput and
performance. In addition to low latency, the device supports a
max payload
size of 2048 bytes
, enabling the user to achieve even higher throughput.
Data Integrity
The PEX 8632 provides
end-to-end CRC
(ECRC) protection and
Poison
bit
support to enable designs that require
end-to-end data integrity
. PLX also
supports data path parity and memory (RAM) error correction as packets
pass through the switch.
Flexible Register & Port Configuration
The PEX 8632’s 12 ports can be configured to lane widths of x1, x2, x4, x8,
or x16. Flexible buffer allocation, along with the device's
flexible packet
flow control,
maximizes throughput for applications where more traffic
flows in the downstream, rather than upstream, direction. Any port can be
designated as the upstream port, which can be changed dynamically. The
PEX 8632 also provides
several ways to configure
its registers. The device
can be configured
through strapping pins,
I
2
C interface
, host
software, or an optional
serial EEPROM. This
allows for easy debug
during the development
phase, performance
monitoring during the
operation phase, and
driver or software
upgrade. Figure 1 shows
some of the PEX 8632’s
common port
configurations.
Figure 1. Common Port Configurations
PEX 8632
Version 0.8 2007
PEX 8632
x4
8 x2
3 x4
PEX 8632
x8
10 x2
PEX 8632
x8
2 x4
2 x8
PEX 8632
x16
x8
x8
相关PDF资料 |
PDF描述 |
|---|---|
| PEX8632-AA50BCG | PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch |
| PEX8632-AARDK | PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch |
| PEX8648 | PCIe Gen2, 5.0GT/s 48-lane, 12-port PCIe Switch |
| PEX8648-AA50BCG | PCIe Gen2, 5.0GT/s 48-lane, 12-port PCIe Switch |
| PEX8648-AARDK | PCIe Gen2, 5.0GT/s 48-lane, 12-port PCIe Switch |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PEX8632-AA50BCG | 制造商:PLX 制造商全称:PLX 功能描述:PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch |
| PEX8632-AARDK | 制造商:PLX 制造商全称:PLX 功能描述:PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch |
| PEX8632-BB50BIF | 功能描述:外围驱动器与原件 - PCI 32 Lane, 12 Port PCI Express Gen 2 Switch RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PEX8636-16U1DBBRDK | 功能描述:界面开发工具 PEX8636-16U1D Basbrd RDK(x16 Up,20 x1 Dn) RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PEX8636-AA50BCF | 功能描述:外围驱动器与原件 - PCI 36 Lane, 24 Port PCI Express Gen 2 Switch RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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